Table of Contents

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CONTENTS

1.Introduction : 

1.1  Career Growth in VLSI Industry

1.2  The Future of Semiconductor 

2. VLSI Topics

2.1  Semiconductor Job Portal - Intern & freshers  

2.2  Digital Design for Beginners and Professionals

2.3  Career Growth in VLSI Industry

2.4  The Future of Semiconductor 

2.5  Reason for limited entry scope for Freshers in VLSI

2.6  VLSI Industry Update

2,7  List of Semiconductor Companies

2.8  Top 10 VLSI companies

2.9  VLSI Industry Updates

2.10 Engineering Basics

2.11 Open Sourced FREE CAD/EDA VLSI tools 

2.12 List of top 10 companies in Semiconductor - 2021 

2.13 The best top 20 universities for MS in Digital VLSI in USA

2.14 Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar 

2.15 Question Answer on VLSI Semiconductor 

 3. Digital Design:

3.1  Low Power Design Technique

3.2  Reset Removal and Recovery Time 

3.3  AND , OR gate using 2:1 Mux

3.4  Draw a  2 input NAND gate using 2:1 mux

3.5  Low Power design and verification

3.6  Which gate power consumption better than reversible logic gate?

3.7  UPF Example 

3.8  SDC File -  A Sample file for Synthesis

3.9  Pos n Neg edge detector

3.10 Lockup Latches

3.11 Selective Signal dumping in VPD VCS

3.12 Async Reset or Sync Reset for ASIC ?

3.13 Digital PLL

3.14 Complex Number

3.15 DLL and PLL

3.16 How to make XOR gate using NAND

3.17 What is MTBF ?

3.18 One's Complement

3.19 Two's Complement

3.20 Error Correction and Detection - SECDEC

3.21 Running Disparity

3.22 Open Sourced FREE CAD/EDA VLSI tools 

3.23 Type of Adders with Verilog Code

3.24 VHDL operator 

3.25 Asynchronous FIFO with Programmable Depth

3.26 Asic Implementation Design Cycle 

3.27  Comparing AMBA AHB to AXI Bus using System Modeling. 

3.28 Difference between I2C or CAN protocol ? 

3.29  Retention Cells - UPF

4. Semiconductor Interface/Bus Protocols

4.1  List of Protocols (PCIe, USB , etc.)

4.2  I²C (Inter-Integrated Circuit)

4.3  Universal asynchronous receiver/transmitter

4.4  SPI

4.5  PCI-Express - Overview

4.6  Transaction Layer in PCI Express

4.7  Microwire IP Interface 

5. Verilog Tutorial /Crash Course

5.1  Verilog Introduction

5.2  Refreshing your brain with Verilog

5.3  Verilog - Data Types 

5.4  Verilog - Statements  

5.5  Verilog Design Style

5.6  Verilog - System Task

5.7  Verilog Operators

5.8  Verilog - Reserved KeyWords

5.9  Parameterized Modules in Verilog

5.10 Timescale in Verilog

5.11 File Handling in Verilog 

5.12 Blocking and Non-Blocking in Verilog 

6. RTL Design Code 

6.1  Verilog Projects

6.2  RTL Verilog Code for Design

6.3  PCIe_Project_Update

6.4  Verilog Code for the counting number of 1's and 0's 

6.5  Verilog code for Asynchronous and Synchronous Reset Flip-Flop

6.6  Verilog code to detect Pattern

6.7  Verilog Code for Gray to Binary Code Converter

6.8  Verilog code for module 

6.9  Verilog code for FIR FILTER

6.10 Verilog code for parity checker (even parity/odd parity)

6.11 Verilog code square root of a number

6.12 Verilog Code for Round Robin Algorithm

6.13 Verilog Code for Binary to 7-segment LED converter 

6.14 Verilog Code for modules

6.15 Verilog Code for 8-bit ALU

6.16 Verilog Binary to gray code conversion

6.17 Verilog code and FSM design to generating custom waveform 

6.18 Verilog code for Synchronous FIFO ( First In First Out  )

 6.19 SPI Controller 

7. Clock Domain Crossing (CDC)

7.1  Clock Domain Crossing (CDC)

7.2  Convergence , divergence and re-convergence

7.3  CDC - Real time implementation

8. RTL Lint 

8.1  SpyGlass Custom Goal setup

8.2  Synchronizers list dump using SpyGlass Tool

9. STA

9.1  Unateness-> Positive Unate and Negative Unate

9.2  VLSI_EXPERT: Transition Violation in Semiconductor

10. Synthesis

10.1  .lib to/from .db conversion

10.2 fanout report on hierarchy in design in synthesis 

10.3 Physical Aware Synthesis 

10.4 SDC file for DDR memory 

11. Integrated-Circuit Fabrication

11.1 IC Fabrication : Interview Questions / Answers 

12. AHB-AXI Protocol 

12.1 How do split response and retry work for the AHB protocol?

12.2 Comparing AMBA AHB to AXI Bus using System Modeling.

13. PCIe Protocol 

13.1  PCI-Express - Overview

13.2  Transaction Layer in PCI Express

13.3  8b10encoder/decoder

13.4  Running Disparity

14. Solution  :Samir Palnitkar : A Guide to Digital Design and Synthesis 

14.1 Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar 

15. Place holder5

16. DAA

16.1  Left Edge Channel Algorithm for detailed routing

16.2  Dynamic vs Static Timing Analysis

16.3  DAA: Design and Analysis of Algorithm 

16.4  DAA: Design and Analysis of Algorithm - QA 

17. Scripting/Others

17.1  GNOME - Terminal while login in VNC

17.2  Shell Script Tutorial

17.3  GVIM Help

17.4  List of Perl Scripts used in post data processing

18. Interview Preparation

18.1  VLSI Interview Questions

18.2  Generic interview Questions

18.3  Interview question on AXI protocol

18.4  Implementation of Logical Questions 

18.5 Digital Design Interview Question on PCIe express 

18.6  Digital Design Interview Question on Synthesis

 

19. Academic/ Educational Projects with Micro-Architecture and Verilog code

19.1  RoadMap For Academic Projects 

19.2  PCI-Express - Overview

19.3  Transaction Layer in PCI Express

19.4  Microwire IP  

20. Verification

20.1  Key Points in Mixed Signal Design Verification

21. Physical Design

21.1  What is the difference between a DRC and a DRV in VLSI PD?

21.2 Physical Design - Common Questions  

21.3 FILLER CELLS  

22. General Question:

22.1  Logical Question

22.2  APTITUDE Question for Interviews

22B . VLSI Quiz 

22B.1  Quiz1 : Digital Design

23. Non-VLSI Topics:

23.1  Worst Hiring Stories

23.2  You need to remove these 6 items from your resume asap

23.3  Resume Guideline if you are applying for job as a Freshers.

23.4  10 Things to remember while considering the offers from your next employer

23.5  Are you looking for job change ?

23.6  How to negotiate for the best when making a move from your present employer ?

23.7  where an engineer/fresher can get the job ?

23.8 How to start a academic project 

23.9  Team Leadership Score check 

23.10 Team Leadership Question/Answer

23.11 Being productive while working from home 

24. Salary Around the Globe

24.1 Norway Salary - Average salary for Senior Software Engineer in Norway with 10+ years experience? 

24.2  Sweden Salary - An Average salary in Sweden for IT professional  

25. Job Opportunities in Norway 

25.1  Norway Salary - Average salary for Senior Software Engineer in Norway with 10+ years experience? 

25.2  Is it hard to get a job in Norway, as a foreigner?

25.3  Living cost in Norway , compared with India

 

26. Finland Opportunities in IT Sector

26.1  Moving to Finland from India , is it worth ?

27. Funny Posts ( non technical )

27.1 40+ Photos That Evoke a Lot of Curious Questions and Can’t Be Explained

I2C Timing Constraint Examples

Timing Constraint for I2C interface :
The I2C protocol is explained well @I2C_Protocol page ,with the protocol knowledge , one should also be knowing how to constraint the I2C interface and close timing on it's interface. 

Timing Constraint for SPI interface:

I2C timing constraints refer to the timing requirements for the communication between the master and slave devices in an I2C bus. These constraints are critical to ensuring proper operation of the bus. The key timing parameters involved in I2C communication are:

1. SCL (Serial Clock Line) Timing

• SCL High Time (T_high): The minimum time the SCL line must stay high between clock pulses.
• SCL Low Time (T_low): The minimum time the SCL line must stay low between clock pulses.
• SCL Rise Time (T_r): The time it takes for the SCL line to rise from a low to a high state.
• SCL Fall Time (T_f): The time it takes for the SCL line to fall from a high to a low state.

2. SDA (Serial Data Line) Timing

• SDA Hold Time (T_sda_hold): The minimum time that the SDA line must remain stable after the clock pulse edge.
• SDA Setup Time (T_sda_setup): The minimum time that the SDA line must remain stable before the clock pulse edge.
• SDA Rise Time (T_rise): The time it takes for the SDA line to rise from low to high.
• SDA Fall Time (T_fall): The time it takes for the SDA line to fall from high to low.

3. Start and Stop Conditions

• Start Condition (T_start): The timing of the transition from high to low on SDA while SCL is high, indicating the beginning of communication.
• Stop Condition (T_stop): The timing of the transition from low to high on SDA while SCL is high, indicating the end of communication.

4. Bus Free Time (T_buf)

• This is the time required between the stop condition of one transmission and the start condition of the next transmission. It ensures that the bus is idle and free for the next communication.

5. Data Validity

• Data Setup Time (T_data_setup): The time that data on SDA needs to be stable before the clock pulse edge to ensure that it is reliably read by the receiver.
• Data Hold Time (T_data_hold): The time that data on SDA needs to remain stable after the clock pulse edge to avoid corruption of data.

Common Values (Typical I2C speed: 100 kHz, 400 kHz)

• SCL High Time (T_high): > 4.7 µs for 100 kHz, > 1.3 µs for 400 kHz.
• SCL Low Time (T_low): > 4.7 µs for 100 kHz, > 1.3 µs for 400 kHz.
• SCL Rise Time (T_r): ≤ 1000 ns.
• SCL Fall Time (T_f): ≤ 300 ns.
• SDA Setup Time (T_sda_setup): ≥ 250 ns.
• SDA Hold Time (T_sda_hold): ≥ 200 ns (minimum after the clock edge).

Important Considerations:

• These timings depend on the specific I2C standard used (Standard-mode, Fast-mode, Fast-mode Plus, High-Speed mode).
• The tolerances for these timings will be dependent on the clock frequency of the bus. For example, with higher clock speeds (like 400 kHz), the timing constraints are more strict than for slower speeds (like 100 kHz).
• The capacitance on the bus and the drive strength of the devices involved can affect these timing values, especially for the rise and fall times.

Great! Let's go over a few common calculations or scenarios for I2C timing constraints, particularly focusing on parameters like rise time, fall time, and bus speed.

Example 1: Rise and Fall Time Calculation

For I2C, the rise time and fall time depend on the pull-up resistors and the capacitance of the bus. Here’s the basic formula to calculate the rise time:

$$T_r = 0.8473 \times R_{\text{pull-up}} \times C_{\text{bus}}$$

Where:

• $T_r$ = rise time in seconds
• $R_{\text{pull-up}}$ = pull-up resistor value in ohms (Ω)
• $C_{\text{bus}}$ = bus capacitance in farads (F)

Example Calculation:

Let’s say you have the following parameters:

• Pull-up resistor $R_{\text{pull-up}} = 4.7 \, k\Omega$
• Bus capacitance $C_{\text{bus}} = 20 \, pF$

Using the formula:

$$T_r = 0.8473 \times 4700 \times 20 \times 10^{-12}$$

Let me calculate that for you!

Example 2: Data Setup and Hold Times

The setup time (T_setup) is the time the data line (SDA) needs to be stable before the clock line (SCL) changes, and hold time (T_hold) is the time the data line needs to stay stable after the clock edge.

Typically:

• Setup time $T_{\text{setup}}$ is often specified as at least 250 ns.
• Hold time $T_{\text{hold}}$ is typically 200 ns or more.

If your device needs to meet specific constraints, you should ensure the time between clock pulses (SCL) and data (SDA) lines meets the minimum requirements.

The constraints (timing requirements) ensure that the data is transmitted reliably between the master and the slave devices. These constraints govern the timing of signals on the SDA (data line) and SCL (clock line). Below are the key timing constraints for I2C communication at Standard mode (100 kHz) and Fast mode (400 kHz):

Key I2C Timing Constraints

1. SCL Clock Frequency:

   • Standard Mode (100 kHz):
     • Maximum frequency: 100 kHz.
   • Fast Mode (400 kHz):
     • Maximum frequency: 400 kHz.

2. SCL Timing:

   • SCL High Time (T_high):
     • Standard Mode: ≥ 4.7 µs.
     • Fast Mode: ≥ 1.3 µs.
   • SCL Low Time (T_low):
     • Standard Mode: ≥ 4.7 µs.
     • Fast Mode: ≥ 1.3 µs.
   • SCL Rise Time (T_rise):
     • Standard Mode: ≤ 1000 ns.
     • Fast Mode: ≤ 300 ns.
   • SCL Fall Time (T_fall):
     • Standard Mode: ≤ 300 ns.
     • Fast Mode: ≤ 300 ns.

3. SDA Timing:

   • Data Hold Time (T_sda_hold):
     • Minimum: 200 ns after the SCL clock edge.
   • Data Setup Time (T_sda_setup):
     • Minimum: 250 ns before the SCL clock edge.
   • SDA Rise Time (T_rise):
     • Same as SCL Rise Time: ≤ 1000 ns for Standard Mode, ≤ 300 ns for Fast Mode.
   • SDA Fall Time (T_fall):
     • Same as SCL Fall Time: ≤ 300 ns.

4. Start and Stop Conditions:

   • Start Condition Setup Time (T_start):
     • Minimum: 4.7 µs.
   • Stop Condition Setup Time (T_stop):
     • Minimum: 4.7 µs.

5. Bus Free Time (T_buf):

   • Minimum time the bus must remain idle before the next Start Condition:
     • 4.7 µs.

6. Data Validity:

   • Data Setup Time (T_data_setup):
     • Data on SDA must be stable for 250 ns before the clock edge.
   • Data Hold Time (T_data_hold):
     • Data on SDA must remain stable for 200 ns after the clock edge.

7. Total Data Transfer Time (for a given number of bits):

   • The time it takes to transfer one bit of data depends on the clock frequency. At 100 kHz: $$T_{\text{bit}} = \frac{1}{100 \, kHz} = 10 \, \mu s$$
   • Similarly, for 400 kHz: $$T_{\text{bit}} = \frac{1}{400 \, kHz} = 2.5 \, \mu s$$

Key Timing Diagram

Here’s a general overview of how the key signals and constraints behave over time:

1. Start Condition (S): The SDA line is pulled low while SCL is high.
2. Data Bit Transfer: SDA is driven low or high while SCL pulses.
3. Stop Condition (P): The SDA line is pulled high while SCL is high.
4. Idle State: Both SDA and SCL are high, and the bus is free.

Example: Timing Calculation for a 100 kHz I2C Clock

• For 100 kHz (Standard Mode):

  • SCL High Time (T_high): ≥ 4.7 µs.
  • SCL Low Time (T_low): ≥ 4.7 µs.
  • T_bit (Time per Bit): 10 µs.

• For 400 kHz (Fast Mode):

  • SCL High Time (T_high): ≥ 1.3 µs.
  • SCL Low Time (T_low): ≥ 1.3 µs.
  • T_bit (Time per Bit): 2.5 µs.

Summary of Critical Timing Values

Parameter	Standard Mode (100 kHz)	Fast Mode (400 kHz)
SCL High Time (T_high)	≥ 4.7 µs	≥ 1.3 µs
SCL Low Time (T_low)	≥ 4.7 µs	≥ 1.3 µs
SCL Rise Time (T_rise)	≤ 1000 ns	≤ 300 ns
SCL Fall Time (T_fall)	≤ 300 ns	≤ 300 ns
SDA Setup Time (T_sda_setup)	≥ 250 ns	≥ 250 ns
SDA Hold Time (T_sda_hold)	≥ 200 ns	≥ 200 ns
Start Condition (T_start)	≥ 4.7 µs	≥ 4.7 µs
Stop Condition (T_stop)	≥ 4.7 µs	≥ 4.7 µs
Bus Free Time (T_buf)	≥ 4.7 µs	≥ 4.7 µs

Constraints to Remember:

• Clock speed is one of the most important factors influencing timing constraints. Higher clock speeds (e.g., 400 kHz vs 100 kHz) demand stricter rise and fall times, as well as tighter setup and hold times for data signals.
• Bus capacitance and pull-up resistor values can also affect timing (especially for rise/fall times).
• SDA and SCL lines must meet setup and hold times relative to each other to avoid data corruption or errors in transmission.

These constraints help to ensure reliable communication, and violating them may result in incorrect data transfer, bus contention, or timing errors.

Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar

 

Solution : 

Chapter 7 : Behavioral Modeling 

Verilog code for 8b/10b encoder and decoder

8b/10b is used mainly for clock recovery in serial communication. With this coding, the serial line will always get a balanced stream of 0's and 1's which give enough switching of 0's and 1's level on the line. It is called DC balancing.
Using this encoding will result in 25% overhead in the data stream , meaning to transmit 80-bits , you will actually transmit 100-bits.

To understand the encoding/decoding , it is highly recommended to read about the "running disparity".


Note that in the following tables, for each input byte, A is the least significant bit, and H the most significant. The output gains two extra bits, i and j. The bits are sent low to high: a, b, c, d, e, i, f, g, h, and j; i.e., the 5b/6b code followed by the 3b/4b code. This ensures the uniqueness of the special bit sequence in the comma codes.

The residual effect on the stream to the number of zero and one bits transmitted is maintained as the running disparity (RD) and the effect of slew is balanced by the choice of encoding for following symbols.

The 5b/6b code is a paired disparity code, and so is the 3b/4b code. Each 6- or 4-bit code word has either equal numbers of zeros and ones (a disparity of zero), or comes in a pair of forms, one with two more zeros than ones (four zeros and two ones, or three zeros and one one, respectively) and one with two less. When a 6- or 4-bit code is used that has a non-zero disparity (count of ones minus count of zeros; i.e., −2 or +2), the choice of positive or negative disparity encodings must be the one that toggles the running disparity. In other words, the non zero disparity codes alternate.
Below is the code for encoder and decoder. Contact me for the soft copy of RTL code.

Encoder Implementation Details ->

Implementation will be based on LUT which can be found in PCIe Specification.

Encoder Pin Descriptions

Name	Type	Descriptions
Clk	I	Encoder Clock. This pin is the main clock of the encoder. All registered inputs and outputs of the encoder are based on the rising of this clock.
Rstn	I	Active Low reset
Data_in[7:0]	I	8-bit data input
kchar	I	Control input
disp_in	I	Running Disparity Input. This pin provides to the encoder the running disparity before the encoding of current 8-bit data on datain_8b bus. 0 - -ve disparity 1 - +ve disparity
data_out[9:0]	O	Encoded data out
disp_out	O	Running disparity output
err	O	Invalid control character requested

Verilog code for 8b/10b encoder
-------------- Verilog Code Start ----------------
WIP

-------------- Verilog Code End  ----------------

Verilog code for 8b/10b decoder
-------------- Verilog Code Start ----------------
WIP 

-------------- Verilog Code End  ----------------

Testbench for the Verilog code , Instantiated encoder and decoder. 

Thanks for visiting the Blog , please share your comments.

Ref - https://en.wikipedia.org/wiki/8b/10b_encoding

IC Fabrication : Interview Questions / Answers

1.Define an Integrated circuit.
An integrated circuit(IC) is a miniature ,low cost electronic circuit consisting of active and passive components fabricated together on a single crystal of silicon.The active components are transistors and diodes and passive components are resistors and capacitors.

2.What are the basic processes involved in fabricating ICs using planar technology?

1.Silicon wafer (substrate) preparation
2.Epitaxial growth
3.Oxidation
4.Photolithography
5.Diffusion
6.Ion implantation
7.Isolation technique
8.Metallization
9.Assembly processing & packaging

3.List out the steps used in the preparation of Si – wafers.

1.Crystal growth &doping
2.Ingot trimming & grinding
3.Ingot slicing
4.Wafer policing & etching
5.Wafer cleaning

4.Write the basic chemical reaction in the epitaxial growth process of pure silicon.
The basic chemical reaction in the epitaxial growth process of pure silicon is the hydrogen reduction of silicon tetrachloride.

SiCl4 + 2H2 <•••••1200oC ••••••> Si + 4 HCl



5.What are the two important properties of SiO2?

1.SiO2 is an extremely hard protective coatng & is unaffected by almost all reagents except by hydrochloric acid. Thus it stands against any contamination.
2.By selective etching of SiO2 , diffusion of impurities through carefully defined windows in the SiO2 can be accomplished to fabricate various components.

6.Explain the process of oxidation.
The silicon wafers are stacked up in a quartz boat & then inserted into quartz furnace tube. The Si wafers are raised to a high temperature in the range of 950 to 1150oC & at the same time, exposed to a gas containing O2 or H2O or both. The chemical action is

Si + 2H2O •••••••••••> SiO2+ 2H2


7. What are oxidation induced defects in semi conductor?

1.Stacking faults
2.Oxide isolation defects

Stacking faults:
Structural defects in the silicon lattice is called oxidation induced stacking faults. The growth of stacking faults is a strong function of substrate orientation , conductivity type & defect nuclei present. The stacking faults formation can be suppressed by the addition of HCl.

Oxide isolation defects :
The stress along the edges of an oxidised area produce severe damage in the silicon. Such defects results in increased leakage in nearby devices. High temperatures (around 950oC ) will prevent stress induced defect formation.


8.What is lithography?
Lithography is a process bywhich the pattern appearing on the mask is transfered to the wafer.It involves two steps: the first step requires applying a few drops of photoresist to the surface of the wafer & the second step is spinning the surface to get an even coating of the photoresist across the surface of the wafer.


9.What are the different types of lithography? What is optical lithography?
The different types of lithography are :

1.Photolithography
2.Electron beam lithography
3.X ray beam lithography
4.Ion beam lithography

5.Optical lithography:

10.What are the two processes involved in photolithography?

a) Making a photographic mask
b) Photoetching

The development of photographic mask involves the preparation of initial artwork and its reduction , decomposition of initial artwork or layout into several mask layers. Photoetching is used for the removal of SiO2 from desired regions sothat the desired impurities can be diffused.

11.Distinguish between dry etching & wet etching.
Dry etching

1.Gaseous mixture is used as the chemical reagent.

2.Smaller line openings( 1µm) are possible with dry etching

3.It produces straight walled etching process.

Wet etching

Chemical reagents used are in the liquid form.

Line opening are larger.(> 1µm)

It produces patterns with undercutting.

12.What is meant by reactive etching?
The term reactive plasma is meant to describe a discharge in which ionization & fragmentation of gases takesplace & produce chemically active plasma species, frequently oxidizers and reducing agents. Such plasmas are reactive both in the gas phase & with solid surfaces exposed to them. When these interactions are used to form volitile products so that material is removed or etching of material form surfaces that are not masked to form lithographic patterns , the technique is known as reactive plasma etching.


13.What are isotropic & anisotropic etching processes?
Isotropic etching is a wet etching process which involves undercutting.
Aisotropic etching is a dry etching process which provides straight walled patterns.

14.Define diffusion.
The process of introducing impurities into selected regions of a silicon wafer is called diffusion. The rate atwhich various impurities diffuse into the silicon will be of the order of 1µm/hr at the temperature range of 900oC to 1100oC .The impurity atoms have the tendency to move from regions of higher concentrations to lower concentrations.


15.What is dielectric isolation?
In dielectric isolation, a layer of solid dielectric such as SiO2 or ruby completely surrounds each components thereby producing isolation , both electrical & physical. This isolating dielectric layer is thick enough so that its associated capacitance is negligible. Also, it is possible to fabricate both pnp & npn transistors within the same silicon substrate.


16.What are the advantages of ion implantation technique?

1. It is performed at low temperature. Therefore, previously diffused regions have a lesser tendency for lateral spreading.

2. In diffusion process, temperature has to be controlled over a large area inside the oven, whereas in ion implantation process, accelerating potential & beam content are dielectrically controlled from outside.

17.What is metallization?
The process of producing a thin metal film layer that will serve to make interconnection of the various components on the chip is called metallization.

Table of Contents

Digital Design Interview Question on Synthesis

Tips to start a Academic project from scratch to completion

Many students ask , what are the steps to start a academic project , I understand , many people like to learn many things , for example , bus protocols (AHB,AXI, PCIe,USB , etc ) , there are so many of things to learn if someone wishes to do.

Here are the steps to start :

1. Decide a Topic/Subject

This should be based on your future goal and should be align with your current career.

2. Once project topic is decided, you can start collecting the material, like specification, IEEE papers , collect as much as information you can and sort it out , and start reading on the project topic.

3. DO NOT GO for coding directly.

4. Start writing the design specification , we call it micro-architecture

6. First make the input/output interface, findout what are the signals available.

7. Make sure you get good knowledge on it before writing down the specification.

8. Once your top level block diagram is ready, then start thinking about the sub-blocks.

9. This will keep going on , by writing a design-specification, your 60% job is done !! Yeah !!

10.Once specification is done, you can start writing the code.

11.Once code is dome, you can write down the testing logic also.

After step 11, your project would be 100% complete.. 

Few useful links 

Academic Projects Activities

Table of Contents

VLSI_EXPERT: Transition Violation in Semiconductor

Max transition (clock or data) is the maximum slew that is allowed at the cell input pin.
This comes either from the library, or it can come from a manually constrained file from the designer.
Similarly, max capacitance check limits the allowed capacitance on the output pin of a cell.

The transition time of a net becomes the time required for its driving pin to change logic values (from 10% (20%) to the 90% (80%) of its maximum value). This transition time used for delay calculations are based on the timing library (.lib files).

Input transition and output load are used to characterize delay through a circuit. Typically, a circuit is simulated under many different process, temperature and voltage conditions over a range of input transitions and output loads to characterize circuit performance. Some design teams prefer to model very accurate delays over a tight range of variables while others can afford to sacrifice some accuracy to accommodate a wider range of performance, e.g. a NAND gate simulated over input transitions from 5ps to 90ps and output loads from 3fF to 200fF could have a more accurate result than one characterized over 0ps to 1ns inputs and 0fF to 1pF outputs.

These are important checks in the timing drcs. Max transition (clock or data) is the maximum slew that is allowed at the cell input pin.This comes either from the library, or it can come from a manually constrained file from the designer.
Similarly, max capacitance check limits the allowed capacitance on the output pin of a cell.

Flagging these and fixing them help with lower dynamic leakage (short circuit current) and reaching more reliability.

Fixing Transition Violation
1. Up sizing the driver cell.
2. Decreasing the net length by moving cells nearer or reducing long routed net.
3. By adding buffers.
4. By using existing spare cells as buffers.
5. By splitting loads through buffers to reduce the fan out number (number of driven cells)



Table of Contents

List of Semiconductor Companies

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HP Inc.	https://jobs.hp.com/search-results/
Intel Corporation	https://www.intel.com/content/www/us/en/jobs/jobs-at-intel.html
Microsoft Corporation	https://careers.microsoft.com/
Renesas Corporation	https://jobs.renesas.com/
STMicroelectronics	https://www.st.com/content/st_com/en/about/careers.html
Texas Instruments	https://careers.ti.com/
ACON, Advanced-Connectek, Inc.	http://www.acon.com/en-global/career/index/13
Advanced Micro Devices	https://careers.amd.com/
Allion Labs, Inc.	https://www.allion.com/recruiting/
Analogix Semiconductor, Inc.	https://www.analogix.com/about-us/careers
Anritsu Corporation	https://www.anritsu.com/en-in/about-anritsu/employment/current-vacancies
ASMedia Technology Inc.	https://www.asmedia.com.tw/careers
Avery Design Systems, Inc.	https://www.avery-design.com/company/careers/
BitifEye Digital Test Solutions GmbH	https://www.bitifeye.com/about-us-4-2/jobs/
Bizlink Technology, Inc.	https://www.bizlinktech.com/careers
Cadence Design Systems, Inc.	https://www.cadence.com/en_US/home/company/careers.html
Corigine, Inc.	https://www.corigine.com/careers.html
Corning Optical Communications LLC	https://www.corning.com/in/en/careers.html
Cypress Semiconductor	https://www.infineon.com/cms/en/careers/
Dell Inc.	https://jobs.dell.com/
Diodes Incorporated	https://www.diodes.com/about/careers/
DisplayLink (UK) Ltd.	https://www.synaptics.com/careers
DJI Technology Co., Ltd.	https://we.dji.com/
Electronics Testing Center, Taiwan
Elka International Ltd.	https://www.elka.com/
Ellisys	https://www.ellisys.com/company/jobs.php
Etron Technology  Inc.	https://etron.com/careers/
Foxconn / Hon Hai	https://recruit.foxconn.com/isite-web/mbMain.changeLang.do?selLang=EN
Fresco Logic Inc.	https://www.linkedin.com/company/fresco-logic
Genesys Logic, Inc.	https://www.genesys.com/en-sg/company/careers
Google Inc.	https://careers.google.com/
Granite River Labs	https://www.graniteriverlabs.com/en-us/careers
Hotron Precision Electronic Ind. Corp	http://www.hotron-ind.com/en/
I-PEX (Dai-ichi Seiko)	https://cms-www.i-pex.com/who-we-are
Japan Aviation Electronics Industry Ltd.	https://www.jae.com/en/
JMicron Technology Corp.	https://www.jmicron.com/
Kandou Bus SA
Keysight Technologies Inc.	https://www.keysight.com/in/en/home.html
L&T Technology Services	https://www.ltts.com/careers
LeCroy Corporation	https://teledynelecroy.com/
Lenovo	https://jobs.lenovo.com/
LG Electronics Inc.	https://www.lg.com/global/careers/career
Lintes Technology Co., Ltd.	https://en.lintestech.com/contact/
Lotes Co., Ltd.	https://www.lotes.cc/
Luxshare-ICT	https://en.luxshare-ict.com/join/index.html
Maxio Technology (Hangzhou) Ltd.	http://www.maxio-tech.com/?cur_lang=en
MediaTek Inc.	https://careers.mediatek.com/
MegaChips Corporation	https://www.indiajobvaccancies.com/jobs-in-megachips-corporation.html
Mercedes-Benz Research & Development, North America, Inc.	https://www.mercedes-benz.co.in/passengercars/the-brand/career.html
Microchip Technology Inc.	https://careers.microchip.com/
Molex LLC	https://jobs.kochcareers.com/search/molex/jobs/in
MQP Electronics Ltd.	https://www.mqp.com/
Newnex Technology Corp.	https://www.newnex.com/
NVIDIA	https://www.nvidia.com/en-in/about-nvidia/careers/
NXP Semiconductors	https://www.nxp.com/company/about-nxp/careers:CAREERS
Oculus VR LLC	https://www.metacareers.com/areas-of-work/oculus/
ON Semiconductor	https://www.onsemi.com/careers
Parade Technologies Inc.	https://www.paradetech.com/jobs/
Phison Electronics Corp.	https://www.phison.com/en/company/career
Qualcomm Inc	https://www.qualcomm.com/company/careers
Realtek Semiconductor Corp.	https://www.realtek.com/en/41-category-en/c-careers-en
Rohde & Schwarz GmbH & Co. KG	https://www.rohde-schwarz.com/in/career/overview/career_233504.html
Samsung Electronics Co. Ltd.	https://www.samsung.com/in/about-us/careers/
Seagate Technology LLC	https://seagatecareers.com/
Silicon Line GmbH	https://www.silicon-line.com/careers/
SiliConch Systems Private Limited	https://www.siliconch.com/careers.php
Softnautics LLP	https://www.softnautics.com/careers/
Spectra7 Microsystems Corp.	https://www.spectra7.com/careers
Specwerkz	https://swzd.com/careers/
STMicroelectronics	https://www.st.com/content/st_com/en/about/careers.html
Sumitomo Electric Ind.  Ltd. Optical Comm. R&D Lab	https://sumitomoelectric.com/careers
Synaptics Inc.	https://www.synaptics.com/careers
Synopsys  Inc.	https://www.synopsys.com/careers.html
Tektronix Inc.	https://careers.fortive.com/tektronix/home
Thine Electronics Inc.	https://www.thine.co.jp/en/corporate/jobs/
Tyco Electronics Corp., a TE Connectivity Ltd. company	https://careers.te.com/
Varjo Technologies	https://varjo.com/jobs/
VIA Labs Inc.	https://www.via-labs.com/careers.php
VIA Technologies Inc	https://www.via-labs.com/careers.php
Weltrend Semiconductor	http://www.weltrend.com/en-global/career
Western Digital	https://jobs.westerndigital.com/
Wilder Technologies	https://www.wilder-tech.com/en/careers
Faststream Technologies	https://www.faststreamtech.com/company/jobs/
Infineon Technologies India Pvt. Ltd	https://www.infineon.com/cms/en/careers/
Saankhya Labs	https://saankhyalabs.com/careers/
Semtronics Micro Systems	https://www.instahyre.com/jobs-at-semtronics-micro-systems/
SmartPlay Technologies
Terminus Circuits	http://www.terminuscircuits.com/careers/
Vayavya Labs	https://vayavyalabs.com/careers/
Alliance Semiconductor (India) Pvt. Ltd.
Analog Devices (India) Pvt. Ltd.	https://www.analog.com/en/about-adi/careers.html
Arcus Technology Pvt. Ltd.	https://www.linkedin.com/company/arcus-technology
Axes Technologies (India) Pvt. Ltd.
Apex Technologies pvt.ltd.
Apara Design Automation Pvt.ltd	http://www.icon-dapl.com/
Broadcom	https://www.broadcom.com/company/careers
CMOS Chips
Cisco Systems (India) Pvt. Ltd.	https://www.cisco.com/c/en/us/about/careers.html
Semiconductors India Pvt. Ltd.
D’GIPRO Systems Pvt. Ltd.	http://dgipro.com/
Digital-X (India) Pvt Ltd.	https://www.digitalx.com/
Digital Equipment India ltd.	https://www.linkedin.com/company/digitalequipmentltd
Digipro Design Automation	http://dgipro.com/
Future Techno Designs Pvt. Ltd.	Closed
GPS Usha Pvt. Ltd.	https://www.usha.in/careers.php
GDA Technologies	https://www.naukri.com/gda-technologies-jobs-careers-4136
GE India Technology center	https://www.ge.com/in/careers
Godrej & Boyce Mfg. Co. Ltd	https://www.godrej.com/godrejandboyce/gnb-careers
HiQ Networks (India) Pvt. Ltd.	https://www.hiqelectronics.com/jobs/
IBM Global Services India Pvt. Ltd.	https://www.ibm.com/careers/in-en/
Lucent Technologies India Ltd.	https://www.al-enterprise.com/en/company/about-us/careers
Motorola India Electronics Ltd.	https://www.motorolasolutions.com/en_xp/about/careers.html
NatSem India Designs Pvt. Ltd.	https://www.zaubacorp.com/company/NATSEM-INDIA-DESIGNS-PRIVATE-LIMITED/U67120KA1995PTC018344
Ncore Technology Pvt. Ltd.	https://www.nkorrtechnologies.com/
Philips SemiconductorsBangalore	https://www.nxp.com/company/about-nxp/careers:CAREERS
Sage Design Systems (India) Pvt. Ltd.	https://sageuniversity.edu.in/Career
Sanyo LSI Technology India Ltd.	https://in.linkedin.com/company/sanyo-india-pvt-ltd-
Siemens Public Communications	https://new.siemens.com/global/en/company/jobs/search-careers.html
Silicon Automation Systems (India) Pvt. Ltd. (SASI)	http://www.sme.in/silicon/
Spike Technologies (India) Pvt.Ltd.	http://spiketech.in/
Shonk Technologies ltd
Tata Elxsi Ltd.	https://www.tataelxsi.com/careers-experience
Texas Instruments (India) Ltd.	https://careers.ti.com/about-us-ti-india/
ThinkIT (India) Pvt. Ltd.	https://www.thinkitive.com/company/careers.html
TVSE
U&I Scotty Computers Pvt. Ltd.	https://ui.talentlyft.com/
Vedatech India (Software) Pvt. Ltd.	https://www.naukri.com/veda-tech-recruiters
Veriphone	https://www.verifone.com/en/careers
Wipro Ltd.	https://careers.wipro.com/careers-home/
Sasken Communication Technologies	https://careers.sasken.com/
Ittiam Systems	https://www.ittiam.com/careers/
SoftJin Technologies Pvt. Ltd.	https://www.timesjobs.com/jobs/accounting-tax-jobs-in-softjin-technologies-pvt-ltd
Jataayu Techosolutions  Pvt. Ltd.	https://in.linkedin.com/company/jataayu-software
Infosys	https://career.infosys.com/
Prestige Meridian-l
Insilica Semiconductors Pvt.Ltd.	https://www.linkedin.com/company/insilica
Adroit IC Design	http://www.adroitgroup.com/careers.php
Agilent Technologies	Bangalore
Altera	Bangalore
AMD	Hyderabad
Analinear Technologies	Hyderabad
Analog Devices	Bangalore
Arasan Chip System	Bangalore
ARM	Bangalore
Atheros	Chennai
Atmel	Chennai
Beceem	Bangalore
BlackPeppertech	Bangalore
Broadcom	Bangalore
Brocade	Bangalore
CGCoreEL	Bangalore
Cirrus logic	Bangalore
Cisco	Bangalore
Concept2Silicon	Bangalore
Cosmic circuits	Bangalore
CVC	Bangalore
Cypress Semiconductors	Bangalore
einfinitus	Bangalore
Einfochips	Bangalore
EVE	Bangalore
Firstpass-semi	Hyderabad
Freescale semiconductors	Bangalore
GD micro	Bangalore
IBM	Bangalore
IDT	Bangalore
Ikanos communications	Bangalore
Infinera	Bangalore
Infenion	Bangalore
Insilica	Bangalore
Intel	Bangalore
Interra systems	Bangalore
Ittiam	Bangalore
Juniper Networks	Bangalore
Karmic	Bangalore
Kasura Technologies	Bangalore
Kawasaki Micro	Bangalore
KPIT Cummings	Bangalore
Lattice Semiconductor	Bangalore
LSI	Bangalore
Magnachip not in india	Bangalore
Mbitwireless	Bangalore
Microchip	Bangalore
Micronas not in india	Bangalore
Mindspeed	Hyderabad
MindTree	Bangalore
Mirafra Technologies	Bangalore
MRO-TEK	Bangalore
Moschip Semiconductors	Bangalore
Mosys	Hyderabad
National Semiconductor	Bangalore
Encore	Bangalore
Netlogicmicro	Bangalore
nvidia	Bangalore
NXP Semiconductors	Bangalore
Open-silicon	Bangalore
Orca systems	Bangalore
Ordyn	Bangalore
Perfectus	Bangalore
picoChip	Bangalore
PMC sierra	Bangalore
Qlogic	Bangalore
Qthink Technologies	Bangalore
Qualcomm	Bangalore
Rambus	Bangalore
Rancore Technologies	Bangalore
Redpine Signals	Hyderabad
Rensas	Bangalore
Sasken communications	Bangalore
Sandisk	Bangalore
Samsung	Bangalore
Scolish Technologies	Bangalore
Semindia	Hyderabad
Sibridge Technologies	Bangalore
Silabs not in india	Bangalore
Silicon hive	Bangalore
Smart-dv	Bangalore
Smartplay	Bangalore
Soctronics	Hyderabad
ST Microelectronics	Bangalore
Tanmic	Bangalore
Tata Elixi	Bangalore
TCS	Bangalore
Tejas networks	Bangalore
Teranetics	Bangalore
Texas instruments	Bangalore
Transwitch	Bangalore
Tundra semiconductors	Hyderabad
Vinchip Systems	Bangalore
Vitesse semiconductors	Bangalore
Whizchip	Bangalore
Wipro	Bangalore
Xambala	Bangalore
Xilinx	Hyderabad
Zarlink Semiconductor	Bangalore
Signoff Semiconducto	Bangalore
Some more are in Hyderabad location.
AMD	Hyderabad
ams OSRAM ( formerly Austria micro systems)	Hyderabad
Broadcom Inc.	Hyderabad
Blaize (formerly ThinCI)	Hyderabad
Intel Corporation	Hyderabad
Imagination Technologies	Hyderabad
Marvell Technology	Hyderabad
Micron Technology	Hyderabad
Microchip Technology Inc.	Hyderabad
NVIDIA	Hyderabad
NXP Semiconductors	Hyderabad
Qualcomm	Hyderabad
Silicon Labs	Hyderabad
Siemens EDA (Siemens Digital Industries Software) formerly Mentor	Hyderabad
Synaptics Incorporated	Hyderabad
Synopsys Inc	Hyderabad
Xilinx (Now AMD)	Hyderabad
Start up companies:
Axiado Corporation	Start-Up
BrainChip	Start-Up
Ceremorphic, Inc.	Start-Up
Kinara, Inc. (formerly Deepvision Inc)	Start-Up

Main Contents 

semiconductor startups in india 

Top 10 semiconductor companies in India 

Top semiconductor companies