Digital PLL

A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal.

VCO ->  Voltage Controlled Oscillator
The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is "fed back" toward the input forming a loop.

Basic architecture of PLL -> 

There are certain limitation in digital to implement it in digital logic , one I can think of is the high frequency. To generate a target frequency , VCO may run at higher frequency which typically in Ghz and digital circuit can not run at such a high frequency. 

There are various method to do the calibration. Few of them are listed below.

1. Through binary search algorithm 

Understand it through an example. (Note -> all values/parameters are logical for understanding purpose )

Below are the parameters available. 

Ref clock -> 250 MHz  (just to make calculation simple, typical ref clock is ~100MHz) 

Target frequency and ref frequency is same, So in given time frame, counter value can be compared to adjust the voltage of VCO to increase/decrease frequency. Below is the calculation.

VCO voltage range -> 0.0 V to 5.0V  , Digital range is 8-bit value ('h0 -> 0.0 V , 'hFF -> 5.0V)

In frequency , 0.0V  -> 0hz , 5.0V -> 4 Ghz 

Target Frequency -> 250Mhz   (Target VCO voltage -> 3.5 V  ->  [2Ghz / Freq_DIV ('d8)] ) 

To start algorithm ->  Will take the middle digital value which will convert into voltage in VCO through DAC.  Signal name ->  vco_val[7:0]  

Start value vco_val ->  8'h80    ,  VCO voltage -> 2.5 V , Frequency generated by VCO -> 1.5Ghz

After Phase Detection and filter logic , 

When this value compared with ref value, result will increase frequency (means increase voltage).

Pictorial View of frequency, converging into Target Frequency.

Pros/Con for this Algorithm ->

Pros :
1. Algorithm is fast , number of iteration will be less if compared with other method.

Con :
1. Additional logic/hardware required to do the calculation.
2. Since there will be large voltage difference during 1st few iteration, this could be an issue in analog component , check with analog designer.

2. Maintaining Step size with FSM 

There could be 2 or more steps with this type of algo. Basically with a known step size (voltage increment or decrements to increase or decrease frequency in VCO ) , moving towards closure to target frequency and then reduce step size to reach more closure of target frequency. There are pros and con doing this.

Major Component in Digital PLL 

1. Phase Detector
2. Filter
3. Phase controller
4. Frequency Divider

1. Phase Detector
This block detect the phase of ref signal and output signal from frequency divider. It generate Lead/Lag signal based on the phase difference.

2 Filter
Filter is required to filter out the unwanted pulse.

3. Phase controller
Phase controller get feedback from Filter , based on the feedback , phase controller can increase or decrease the frequency and wait for next feedback.

4. Frequency Divider

Since system clock will be running at much higher frequency , To get the target frequency , frequency divider should be programmed correctly. It is normally configurable and configure at the beginning of calibration. through out calibration , it is constant. 

Verilog Code for Digital PLL

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