Comparing AMBA AHB to AXI Bus using System Modeling.

Comparing AMBA AHB to AXI Bus using System Modeling.

Embedded system designers have a choice of using a shared or point-to-point bus in their designs. 

Typically, an embedded design will have a general purpose processor, cache, SDRAM, DMA port, and Bridge port to a slower I/O bus, such as the Advanced Microcontroller Bus Architecture (AMBA) Advanced Peripheral Bus (APB). 

In addition, there might be a port to a DSP processor, or hardware accelerator, common with the increased use of video in many applications. 

As chip-level device geometries become smaller and smaller, more and more functionality can be added without the concomitant increase in power and cost per die as seen in prior generations. 

System Modeling is a new methodology above the detailed chip implementation level that allows one to explore different designs without having to write Verilog, System Verilog, VHDL, SystemC, or just plain C/C++ code. This saves considerable development time, and allows for more design exploration prior to selecting a design topology to begin implementation. 

This paper discusses the construction of an AMBA Advanced High-performance Bus (AHB) Shared Bus and AMBA Advanced eXtensible Interface (AXI) point-to-point Bus using a graphical modeling environment that achieved approximately 95% cycle accuracy. 

The graphical model and simulation analysis was completed in approximately one week.

To make the evaluation of the two busses comparable in terms of flow, throughput and latency, the following considerations were adopted:

1. 

The AHB is a single-channel, shared bus. The AXI is a multi-channel, read/write optimized bus. Each bus master, or requesting bus port, connects to the single-channel shared bus in the AHB, while each AXI bus master connects to a Read address channel, Read data channel, Write address channel, Write data channel, and Write response channel. The primary throughput channels for the AXI are the Read/Write data channels, while the address, response channels are to improve pipelining of multiple requests. Assume there are four masters on each bus going to three slaves. The four master ports might include uProcessor, Direct Memory Access (DMA), DSP, USB. The three slaves might include on-chip RAM, off-chip SDRAM, and an APB bus bridge.

2. 

To approximate the bandwidth of the two busses, one must count the number of read/write channels of the AXI Bus – six for three bus slaves. This suggests that the AHB Bus should support some multiple of bus width and/or speed to match the data throughput. The System Model can vary these combinations with simple parameter changes, however, the AHB bus speed was assumed to be double the AXI Bus, and two times the width. This will make the comparison of the two busses more realistic.

3. 

To evaluate the efficiency of both busses, different burst sizes were selected; small, medium, and large. Small equates to the width of the AHB Bus, medium equates to two AHB Bus transfers, and large equates to four AHB bus transfers.

4. 

If the AXI is a 64 bit bus running at 200 MHz, then the AHB will be a 128 bit bus running at 400 MHz. The burst sizes will be: small (16 Bytes), medium (32 Bytes), and large (64 Bytes).

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