Gate Level Simulation

Below are the basic question which should come in your mind if you are new to gate level simulation.

What is gate level simulation and why do we need to run it ? 

Performing gate-level simulation gives us the opportunity to check that our circuit still works properly after

being Synthesized and Placed and Routed. Additionally, we use the gate-level simulations to obtain switching

activies for each gate in the design. This will allow us to estimate power and energy.

In a broad view, Gate level simulation is required to check all gates are meeting their respective required timing or not , it is dynamic timing analysis. 

There are 2 types of timing analysis, static timing analysis and dynamic timing analysis.

In Static Timing Analysis , we are checking timing on the paths which on in same clock domain , STA Tools are not able to do timing analysis on the path which are having different lunch and capture clocks , as there is no phase relationship and called asynchronous paths.

But those path can be check in Gate Level Simulation. 

Gate level simulation can be run in two phases , 

1. After synthesis or before place and route 

2. After place and route 

One can reuse the same verification environment as used during functional verification,  in Gate Level simulation, there is no need to run full regression , but one should choose the testcase which cover almost all scenario. 

If GLS (gate level simulation) is running after place and route then one has to annotate SDF (standard delay format) file. There are different ways to annotate SDF file in simulation , one should confirmed in simulation for a successful annotation by looking in waveform. 

Below are the commands to annotate SDF file - 

Using system task -
$sdf_annotate("SDFFILE", "Instance" , , "log_file.log", "minimum or typical or maximum" ); 

For Example - to specify maximum delay values:
$sdf_annotate("myasic.sdf", testbench.u1, , , "maximum");

$sdf_annotate must be in "initial" block.

Above system task can be defined from the top level simulation module (most probably testbech where DUT is instantiated) , and in that case , one should defined the instance in system task where SDF file is made. Be default tool will consider the instance where this system task is called.

There is other way to annotate SDF , which is simulator dependent.

For Modelsim Simulator - 

vlog  <netlist> <tech_lib>
vsim -sdfmax /testbench/u1=myasic.sdf testbench

-sdfmax , -sdfmin , -sdftyp are the corners to check max/min/typ delays in simulation.

For NC-Verilog Simulator -

Compiling the SDF file - 

ncsdfc -messages <file.sdf> -output file_sdf.compiled 

If SDF file size is very large then zip it before compiling and give below command - 

gzip file.sdf 

ncsdfg file.sdf.gz -output file.sdf.compiled 

There are different ways to annotate SDF file , but the simplest one is to use $sdf_annotate task with in a module.
In this task , one can define the configuration file also where specific parameters can be passed to simulation (example - turn off timing on input delays , interconnect delays , etc)

In ncelab, a command file can be passed to simulator to configure the SDF annotation, but this will again a complex job.

Below options can work in both verilog-XL simulator and modelsim.

-l <filename>
By default, the simulation log is written to the file "transcript". The -l option allows you
to specify an alternate file.

+maxdelays
This option selects the maximum value in min:typ:max expressions. The default is the
typical value. This option has no effect if the min:typ:max selection was determined at
compile time.

+mindelays
This option selects the minimum value in min:typ:max expressions. The default is the
typical value. This option has no effect if the min:typ:max selection was determined at
compile time

+typdelays
This option selects the typical value in min:typ:max expressions. This is the default. This
option has no effect if the min:typ:max selection was determined at compile time.

+no_neg_tchk
This option disables negative timing check limits by setting them to zero. By default
negative timing check limits are enabled. This is just the opposite of Verilog-XL, where
negative timing check limits are disabled by default, and they are enabled with the
+neg_tchk option.

+notimingchecks
This option completely disables all timing check system tasks.

+sdf_verbose
This option displays a summary of the design objects annotated for each SDF file.


For small design , it is ok to run simulation again and again , but for large SoC , it is very difficult to run GLS from starting , it will eat a lot of simulation time as well as your time.
There are options where you can reduce the simulation time , for example , keep compiled version of all source file and SDF file , whenever you are running GLS , you can just load the compiled files in simulator.

Think carefully if planning to run simulation again for large SoC.


Upcoming topics -
Standard delay format 
Different types of delays in design 

Hope this will clear some of doubts , if there are anything I can help you, please leave in comments , I will try my best level to put some specific information here.

Thanks for your valuable time.

Rahul Jain