Low Power Design and Verification

Low power design is not a new area, but it was not that much important as it is now.
Semiconductor market trend is very fast changing , and it is a challenge to face and ready with new technology.

The low power design , these days it is important because technology is now getting saturated with 28 nm , if you go below of that then device will be more costlier. So now in coming days people will move into low power design, the other reason is , as you go from 160um to 28um,  power dissipation was not much on 90 or above um technology, but as technology moving into more advanced, power dissipation going higher and higher.

Other reason is , these days we are using battery operated device like cellphone, tablet, laptop, etc , one of the major factor on these device is battery , people want long life for battery  and a good low power design can give you long life battery

Below is the graph showing power trend with respect to time , as we are moving from 2006 to 2020, static power dissipation is more and more , static power dissipation happens when device is in idle state , which means , now a days there are many module which stay ideal most of time.

In CMOS , below is the chart for power consumption -

So .. Where does the power go ?

In SoC design , total power consists of dynamic power and static power.
Dynamic power dissipation is due to signal activity , when signal changing value from 1 to 0 or 0 to 1, there will be power dissipation.
Static power dissipation is due to leakage power and it happen when device is in ideal state.

Dynamic Power Dissipation

Below is the equation to calculate the dynamic power.

                           P(dyn)  =  C*Vdd*Vdd*f
where ..
f -  frequency
Vdd-  Voltage
C - effective capacitance

Dynamic Power depend on clock frequency , power supply , switching activity , transistor width ,length , etc

Static Power Dissipation 
Static power dissipation is due to leakage current. below is a pictorial comparison between dynamic power and static power.

There are few technique used to save power in design, few of them I have mentioned below.

Clock Gating

1. Clock trees are a large source of dynamic power.
2. Clock gating can occur at any level  in design. 
3. Try to put clock gating circuit near to clock source , this will save a significant amount of power. 

Operand Isolation

1. Datapath computation elements are sampled only periodically.
2. Adding one enable signal and control sampling with enable signal.
3. Whenever enable is inactive , datapath inputs can be forced to constant value, this will result in saving dynamic power.

Multi Vth

1. Multiple voltage threshold optimization utilizes gates with different threshold to optimize for power, timing and area constraint. 
2. A good synthesis tool should be able to mix available multi threshold library cells to meet speed and area constraint with low power dissipation.

MSV ( Multi Supply Voltage)

1. Multi-supply voltage techniques operate different blocks at different voltages.
2. Running at a lower voltage reduces power consumption, but at the expense of speed. 
3. Designers use different supply voltages for different parts of the chip based on their performance requirements.
4. MSV implementation is key to reducing power since lowering the voltage has a squared effect on active power consumption.
5. MSV techniques require level shifters on signals that go from one voltage level to another. 
6. Without level shifters, signals that cross voltage levels will not be sampled correctly.

Dynamic Voltage and frequency scaling 

Supply voltage plays a major role power dissipation as it used in calculation in dynamic power as well as leakage power dissipation. Reducing voltage supply will save a lot of power but it will make design work at lower frequency. If you reduced voltage , then this will result in increment of combinational/sequencial delays. Also if design is working at low frequency then power dissipation will be less. This is dynamic power management and may be hardware/firmware control power supply and frequency of design, depends on implementation.

Power Shut-Off  (PSO)

1. One of the most effective technique – called power gating.
2. Switch off the power to parts of chips when blocks are not in use.
3. it can eliminate up to 96% of leakage current.
4. A specific power sequence is needed which includes isolation on signals from the power down domain.

Isolation 

1. Isolation logic is typically used at the output of a powered-down block to prevent floating or unpowered signals from propagating from powered-down blocks.
2. The outputs of blocks being powered down need to be isolated before power can be switched off; and they need to remain isolated until after the block has been fully powered up. Isolation cells are placed between two power domains and are typically connected from domains powered off to domains that are still powered up.

State Retention 

1. To speed-up recovery, state retention power gating flops can be used. 
2. Those flops retain their state while the power is off. 
3. Area of verification is to checking the library specific requirement should be satisfied and flops actually retaining their state.

Memory Splitting

1. In many systems, the memory capacity is designed for peak usage. During normal system activity, only a portion of memory is actually used at any given time.
2. In many cases, it is possible to divide the memory into two or more sections and selectively power down unused section of memory.

Low Power Verification 

Low power verification is having extra effort in verification to verify low power design , there are few area which we can not verify in simulation but there are tools available in market. 

In simulation perspective, below features can be verified - 

1. Power up/Power down sequence 
2. Assertions on boundary 
3. Isolation/Retention cells verification
4. Hardware-Software deadlock 
5. Power-on Reset/ Bring up

UPF (Unified Power Format)  - 

UPF plays a major role in low power design , this is a TCL based script which having information about the power intent of design and specify the power domain.  This file is similar to SDC file , except SDC has timing information and UPF has power related information but syntax totally different in SDC and UPF.  If there are multi supply voltage used in design, then designer will have to create UPF file and put that information into file.

Few points about UPF -

1. IEEE 1801 standard format
2. Extension of Tcl tool command language 
3. Defined separately from HDL
4. Enables early verification 
5. Drive verification and implementation from RTL to layout 

Common command used in UPF 

• create_power_domain
• set_isolation
• set_level_shifter
• set_retention
• create_supply_port
• create_supply_net
• create_power_switch
• connect_supply_net
• add_port_state
• create_pst
• add_ast_state .. etc 

For more detail on UPF , visit below page .. 

UPF (Unified Power Format)

Other Topics -
Contents
Refreshing your brain with Verilog 
Digital Design of Hybrid Memory Cube
Correct way of  Digital design RTL Coding
Clock Gating Circuits
Digital Design Interview Question
Knowledge on Verification
How To debug a simulation
Retention cells 

More are yet to come , all comments and suggestions are welcome and will help to put information here.  

Click to see my Linked-in profile