Static Timing Analysis

STA play an important role during chip development process, it is timing sign off process.



So .. What is STA ?
Static timing analysis (STA) is a simulation method of computing the expected timing of a digital circuit without requiring a simulation of the full circuit. High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate.

Below are the main responsibilities of a STA engineer.

1. Setup Timing violations
2. Hold Timing violations
3. Min Pulse violations
4. Max transition violations
5. Max Cap violations
6. Clock transition violations
7. Clock Gating violations .. etc

Hold timing check can only be done once clock tree netlist is available. Hold time is not dependent on clock frequency.
Setup timing can be check on after synthesis netlist with more margin. It will give initial report about the design.

There could be n number of corners , below is the calculation for corners.

STA run individually in test mode and function mode.

Test Mode ->
These days there could be below test mode.
1. Scan mode
2. At-Speed/Capture mode.
3. OCC scan mode

Functional Mode ->
It depends on the functionality of design. There could be normal mode, loopback mode , few special debugging mode .. , when design is not in test mode, design support one mode at the time.
1. normal mode
2. Loopback mode

PVT conditions ->
1. Fast corner ( best case)
2. Slow corner (worst caese)
3. Fast corner with higher temp
4. Typical
5. combinations of corner 1 and 2

Total corners -> (number of PVT condition) * (Functional Mode) * (Test mode)

Once STA has ran , post processing will required to get the desired result. If using some standard tools which can present a dashboard from STA result , then much scripting may not be required.

Perl/Tcl is majority of script which used in post-processing and building up the environment. Shell can also be used.

You need to have good grip on below unix command.
1. grep
2. compare
3. find
4. awk
5. sed

Under-Construction Pages :
Timing Analysis : Input to output
Timing Analysis : Input to Reg
Timing Analysis : Reg to Reg
Timing Analysis : Reg to Output timing analysis


For go in more detail, go @ below link.

Practical Knowledge on STA

FAQ :
Q1. how to get the unconstrained path in a design ?
A. check_timing -verbose
     report_timing -exceptions
     report_disable_timing

Q2. What is the relationship for the timing analysis and UPF ?
A.  ??



Thanks
Rahul