Handling multiclock domain in design ( RTL + SDC )

In today world, it is most likely design having multiple clocks and there will be signals crossing between those clock domain.  The one way to design such logic is writing FSM in both clock domain and keep request/ack mechanism. Request must be synchronized in destination clock domain and acknowledge must also be sync in destination clock.

Below is the simple example of clock domain crossing , output from flop "FA" is going into "FB" which is clocked by C2. 

Below are few points I remembered while working on multi clock domain.
For synchronization, there are different technique used in industry, they are all standard one.

To synchronize a bus, normally Async FIFO is used. Depth of FIFO will depend on certain parameters like input datarate, output datarate, latency , packet size,etc.

For communication between 2 FSM which are working in different clock domain, request and handshake with 2/3 stage sync cell prefer to use.
There are signals which are pseudo-static , those signal will not required any synchronization those will be static for the duration in which they are getting used :)
Any question/suggestion, please feel free to ask me.
thanks,
Rahul J