Clock Dividers and Multipliers

Q1 How to generate a divide by -N clock ?

Quick Summary (Practical Notes)

• Even divide (N=2,4,6...): easiest using a toggle flop or mod-N counter; duty cycle is naturally 50%.
• Odd divide (N=3,5,7...): exact 50% duty cycle usually needs both posedge and negedge elements (or PLL/DLL).
• Clock divider outputs are clocks: always check glitch-free logic, duty cycle, and half-cycle timing between posedge↔negedge paths.
• Prefer using library clock-gating/clock-divider IP if available; it is safer for CTS and sign-off.

Generate Divide by 2 Clock - 

Below is circuit for Divide by 2 clock , this is nothing but a T-FlipFlop.

Key Facts (Divide-by-2)

• Frequency: Fout = Fin / 2
• Duty cycle: exactly 50% (ideal), because output toggles every clock edge.
• Implementation: 1 flip-flop (T-FF) or D-FF with D = ~Q.
• Use case: common for generating internal slower clocks, test clocks, and simple prescalers.

Divide by 3 Clock with 50% duty cycle - 

To generate divide by 3 clock with 50 % duty cycle, you need to use negedge and posedge flops. There is not much logic between the flops, so signals going from posedge to negedge or negedge to posedge , will not be having any timing issue. Half clock cycle will be sufficient to meet the timing. But if frequency is too high , then check gate timing. Half clock cycle may be close to meet timing.

Design Checks (Divide-by-3, 50% duty)

• Half-cycle constraint: posedge-to-negedge and negedge-to-posedge paths must meet T/2 timing.
• Skew sensitivity: duty-cycle accuracy can degrade with clock skew and asymmetric rise/fall delays.
• CDC warning: if you treat the divided clock as a new clock domain, define proper constraints and crossings.
• Glitch requirement: output must be generated using safe sequential logic; combinational mixing can create spurious pulses.

Most solutions that came in, utilized 4 or 5 flip flops plus a lot more logic than I believe is necessary. The solution, which I believe is minimal requires 3 flops - two working on the rising edge of the clock and generating a count-to-3 counter and an additional flop working on the falling edge of the clock.

Implementation Comparison (Divide-by-3)

Approach	Flops	Duty Cycle	Notes
Simple mod-3 counter	2	Not 50%	Easy but duty cycle not symmetric
posedge + negedge assist (minimal)	3	Near 50%	Half-cycle timing must close
PLL/DLL based	N/A	Excellent	Area/power cost; best for high frequency

Below is block diagram which shows the posedge and negedge flops.

Below is RTL code in Verilog, it is not synthesizable but anyone can make it using reset the flops.

Code Notes (Simulation vs Synthesis)
- The clock generation using "#PERD" is for simulation only.
- For synthesis, drive clk from a real clock pin and use a synchronous reset for the counter and negedge flop.
- Avoid generating clocks with combinational logic in production ASIC flows; prefer enable-based design or integrated clock divider IP.

---------------------------
module clk_div_3;

reg clk=0;

parameter PERD = 10 ;
always #PERD clk = ~clk;
reg [1:0] cnt = 0;
reg cnt_lsb_negedge;

always @(posedge clk)begin
if(cnt == 0)
cnt <= 2;
else
cnt = cnt -1 ;
end
wire cnt_lsb;

assign cnt_lsb = (cnt ==2);

always @(negedge clk)
cnt_lsb_negedge <= cnt_lsb;

real cur_time;
real prev_time;
always @(clk) begin
cur_time <= $time;
prev_time <= cur_time;
end

wire div_3;
assign div_3 = ~((cnt_lsb) || (cnt_lsb_negedge));

endmodule

----------------------------------------------

Divide by 5 Clock - 

To generate div-5 clock , you can use Mod5 counte 3 flops. there are 2 options.
1st option - for mod5 counter , toggle signal in every 3 count and then 2 count , this will give you div5 clock but duty cycle will be 40/60% .

2nd option - for 50% duty cycle, you need one negedge flop to detect negedge after count 1 , assuming counter will start from 0.

So here is the logic -

counter -- 0 ,1 ,2, 3, 4 ,0, 1, 2 ,3 ,4 --- 60 / 40 % duty cycle
counter -- 0 ,1 ,2, 3, 4 ,0, 1, 2 ,3 ,4 ,

at counter value 2, use negedge to detect and then you can use some gates to generate divided by clock.

Rule of Thumb for Odd Dividers (N=3,5,7,...)

• Without negedge logic: you usually get a non-50% duty cycle (example: 40/60 for N=5).
• With negedge sampling: you can align edges and get close to 50% duty cycle, but half-cycle timing becomes critical.
• Higher frequency: consider PLL/DLL if half-cycle paths are too tight or if duty-cycle accuracy is important.

All odd number divider works on same logic, you just need to pick correct counter to generate clock and optimize logic.

You also need to consider the gate delay here, due to combinational gates , a glitch may propagate to design. Draw your circuit on paper and draw waveform out of it. If there is glitch then your clock divider will not work. Make sure there should not be any glitch.


Clock Multiplier 

Normally we use PLL/DLL to generate desire clock frequency, but that will come in cost and area. there are other alternative ways to generate clock multiplication , like multiply by 2, use posedge and negedge of clock. If there is a requirement of precise frequency , you can use delay gates and generate clock out of it.

Practical Notes (Clock Multiplication)

• PLL/DLL: best for precision, jitter control, and duty-cycle correction (but costs area and power).
• Edge-combining (x2): using posedge and negedge can create a pulse train, but be careful: it is not always a clean 2x clock suitable for CTS.
• Delay-chain methods: can be used for simple pulse generation, but are highly PVT sensitive (process, voltage, temperature).
• Recommendation: if the multiplied output is a real clock domain, PLL/DLL is usually the sign-off safe method.

-- Rahul J