Interview question on AXI protocol

Difference between AHB and AXI?

Difference between AXI3 and AXI4?

What is AXI Lite?

Name five special features of AXI?

Why streaming support,it's advantages?

Write an assertion on handshake signals - ready and valid, ready comes after 5 cycles from the start of valid high?

Explain AXI read transaction

What is the AXI capability of data interleaving?

Explain out-of-order transaction support on AXI?

Explain multiple outstanding address pending?

Any flow control mechanism in AXI?

How to ensure data integrity on AXI?

What is 'last' signal?

What are bursts and transfers?

Maximum size of a transfer?

Write response codes?

What is strobing in AXI?

Here is the answer book .. 

Below is a complete, interview-grade explanation of ALL AXI/AHB questions, with simple diagrams + clear descriptions.

This is suitable for VLSI / SoC / IP design interviews and revision.

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1️⃣ Difference between AHB and AXI

AHB (Advanced High-performance Bus)

• Shared bus architecture

• One transaction at a time

• Limited pipelining

AXI (Advanced eXtensible Interface)

• Point-to-point, multi-channel

• Multiple outstanding transactions

• Fully pipelined, high throughput

Diagram

AHB:

Master ----[Shared Bus]---- Slave

AXI:

Master --AR--> Slave

Master <--R--- Slave

Master --AW--> Slave

Master --W---> Slave

Master <--B--- Slave

Key Differences

Feature AHB AXI

Channels 1 5

Performance Medium Very High

Out-of-order ❌ ✅

Outstanding txns ❌ ✅

Flow control Limited Ready/Valid

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2️⃣ Difference between AXI3 and AXI4

Feature AXI3 AXI4

Max burst 16 beats 256 beats

Write interleaving Allowed ❌ Removed

Signal complexity More Reduced

IDs Separate R/W Unified

Efficiency Good Better

👉 AXI4 is simpler and more efficient

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3️⃣ What is AXI Lite?

AXI-Lite is a simplified AXI4 used for control registers.

Characteristics

• No burst

• No ID

• Single transfer only

• Low hardware cost

Use Case

CPU ---> Control Registers (AXI-Lite)

👉 Used for configuration, not data movement.

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4️⃣ Five Special Features of AXI

1. Independent read/write channels

2. Multiple outstanding transactions

3. Out-of-order completion

4. Burst transfers

5. Ready/Valid handshake

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5️⃣ Why Streaming Support? Advantages?

AXI-Stream removes address overhead.

Diagram

Producer --> TVALID/TREADY --> Consumer

Advantages

• Maximum throughput

• Ideal for video, audio, DSP

• Simple protocol

• Low latency

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6️⃣ Assertion: READY after 5 cycles of VALID

property ready_after_5;

  @(posedge ACLK)

    $rose(VALID) |-> ##5 READY;

endproperty

assert property (ready_after_5);

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7️⃣ Explain AXI Read Transaction

Channels Used

• AR – Address

• R – Read data

Diagram

Master           Slave

  |--ARVALID---->|

  |<--ARREADY----|

  |<--RVALID-----|

  |---RREADY---->|

Description

1. Master sends read address

2. Slave returns data

3. Last beat marked using RLAST

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8️⃣ AXI Capability of Data Interleaving

AXI allows multiple read/write transactions to overlap.

Diagram

ID1: Addr ---- Data ---- Data

ID2: Addr ---- Data

👉 Improves bus utilization.

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9️⃣ Out-of-Order Transaction Support

AXI uses Transaction IDs.

Diagram

AR(ID=1) ------>

AR(ID=2) ------>

R(ID=2) <------

R(ID=1) <------

👉 Responses can return in any order.

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🔟 Multiple Outstanding Address Pending

AXI allows sending multiple addresses before data returns.

Diagram

AW1 --->  

AW2 --->  

AW3 --->  

👉 Enables high throughput and pipelining.

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1️⃣1️⃣ Flow Control Mechanism in AXI

Uses READY/VALID handshake

Rule

• Transfer occurs when READY = 1 AND VALID = 1

Diagram

VALID  ─────■■■■■■

READY        ─■■■■■

DATA   --------✔✔✔

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1️⃣2️⃣ How to Ensure Data Integrity on AXI?

1. Handshake mechanism

2. Burst length tracking

3. Response codes

4. Byte strobes

5. LAST signal

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1️⃣3️⃣ What is LAST Signal?

Marks the final beat of a burst

Diagram

Beat1  Beat2  Beat3

DATA   DATA   DATA

LAST           ↑

Signals:

• RLAST – Read

• WLAST – Write

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1️⃣4️⃣ What are Bursts and Transfers?

• Transfer → Single data beat

• Burst → Group of transfers

Burst Types

• FIXED

• INCR

• WRAP

Diagram

Burst of 4:

Addr + Data1 + Data2 + Data3 + Data4

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1️⃣5️⃣ Maximum Size of a Transfer

• Transfer size: Up to 1024 bits (128 bytes)

• Defined by AWSIZE/ARSIZE

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1️⃣6️⃣ AXI Response Codes

Code Meaning

OKAY Normal

EXOKAY Exclusive success

SLVERR Slave error

DECERR Decode error

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1️⃣7️⃣ What is Strobing in AXI?

Uses WSTRB to indicate valid bytes.

Diagram

Data = [B3 B2 B1 B0]

WSTRB= 1  0  1  1

👉 Allows partial writes.

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🎯 Interview Tip

If asked “Why AXI over AHB?”

AXI provides higher throughput, better scalability, and advanced features like out-of-order execution and multiple outstanding transactions.

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