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RTL Digital Design
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Test Yourself VLSI Quiz Hub Digital Design · UPF · Protocols · STA — Sharpen your skills with fresh quizzes1. Introduction
2 links3. Digital Design
28 links- Low Power Design Technique
- Reset Removal and Recovery Time
- AND, OR Gate Using 2:1 Mux
- Draw a 2-Input NAND Gate Using 2:1 Mux
- Low Power Design and Verification
- Which Gate Has Better Power Consumption Than Reversible Logic?
- UPF Example
- SDC File — A Sample File for Synthesis
- Pos / Neg Edge Detector
- Lockup Latches
- Selective Signal Dumping in VPD / VCS
- Async Reset or Sync Reset for ASIC?
- Digital PLL
- Complex Number
- DLL and PLL
- How to Make XOR Gate Using NAND
- What is MTBF?
- One's Complement
- Two's Complement
- Error Correction and Detection — SECDEC
- Running Disparity
- Open Source Free CAD / EDA VLSI Tools
- Type of Adders with Verilog Code
- VHDL Operator
- Asynchronous FIFO with Programmable Depth
- ASIC Implementation Design Cycle
- Comparing AMBA AHB to AXI Bus Using System Modeling
- Difference Between I2C or CAN Protocol?
- Retention Cells — UPF
4. Interface / Bus Protocols
7 links5. Verilog Tutorial / Crash Course
12 links- Verilog Introduction
- Refreshing Your Brain with Verilog
- Verilog — Data Types
- Verilog — Statements
- Verilog Design Style
- Verilog — System Task
- Verilog Operators
- Verilog — Reserved Keywords
- Parameterized Modules in Verilog
- Timescale in Verilog
- File Handling in Verilog
- Blocking and Non-Blocking in Verilog
6. RTL Design Code
20 links- Verilog Projects
- RTL Verilog Code for Design
- PCIe Project Update
- Counting Number of 1's and 0's
- Asynchronous & Synchronous Reset Flip-Flop
- Verilog Code to Detect Pattern
- Gray to Binary Code Converter
- Verilog Code for Module
- Verilog Code for FIR Filter
- Parity Checker (Even / Odd Parity)
- Square Root of a Number
- Round Robin Algorithm
- Binary to 7-Segment LED Converter
- Verilog Code for Modules
- 8-bit ALU
- Binary to Gray Code Conversion
- FSM Design to Generate Custom Waveform
- Synchronous FIFO (First In First Out)
- SPI Controller
- CRC Generator
- Coverage Analysis Guide
7. Clock Domain Crossing (CDC)
3 links8. RTL Lint
2 links9. STA (Static Timing Analysis)
2 links10. Synthesis
4 links11. IC Fabrication
1 link12. AHB-AXI Protocol
2 links13. PCIe Protocol
4 links14. Solution — Palnitkar Guide
1 link16. DAA (Design & Analysis of Algorithms)
4 links17. Scripting / Others
4 links18. Interview Preparation
6 links19. Academic / Educational Projects
4 links20. Verification
1 link21. Physical Design
4 links22. General Questions & VLSI Quiz
12 links23. Non-VLSI Topics
17 links- Worst Hiring Stories
- Remove These 6 Items From Your Resume ASAP
- Resume Guideline for Job Applicants (Freshers)
- 10 Things to Remember While Considering Offers
- Are You Looking for a Job Change?
- How to Negotiate the Best When Making a Move
- Where Can an Engineer / Fresher Get a Job?
- How to Start an Academic Project
- Team Leadership Score Check
- Team Leadership Question / Answer
- Being Productive While Working From Home
- Norway Salary — Senior Software Engineer (10+ yrs)
- Sweden Salary — Average for IT Professional
- Is It Hard to Get a Job in Norway as a Foreigner?
- Living Cost in Norway Compared With India
- Moving to Finland From India — Is It Worth It?
- 40+ Photos That Evoke Curious Questions & Can't Be Explained
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Can u send the documents to ganeshsynopsys@gmail.com
ReplyDeleteSorry, I do not know how to make pdf out of it, there are almost 120 pages I have covered so far and I think it is more user friendly interface to browse ..
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Content seems tummy full...
Its almost 7 years when I started writing , and at present still doing whenever possible.
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ReplyDeletei completed PhD in VLSI DESIGN IN FEB 2021, HOW TO GET JOB IN VLSI INDUSTRY
CAN YOU HELP ME
Great Job Rahul !!!
ReplyDeleteThanks
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