Quiz3 : Digital Design Fundamentals

Contents

1.

Verilog : Which one is perfect example for simulation and synthesis mismatch ?

always @(*)

always @(posedge clk ) { }

always @(a ) { b = a ; }

none

2.

Verilog: with operator "===" ,

Output can be 1,0 or X

Output can be 0 or 1

it is invalid operator

None

3.

Verilog: Which code will implement synchronous reset flop ?

always @(posedge clk or negedge reset) { }

always @(*) { }

always @ (posedge clk ) { }

None

4.

Verilog is a

web designing language

hardware description language

Full Stack developer

None

5.

Which is the case equality operator ?

==

===

!==

!=

6.

Which one is the bit-wise negation operator ?

$

&

~

!

7.

In procedural assignment ,value will assign to

net

wire

register

none

8.

Which one is the gatetype keyword ?

nmos

pmos

cmos

all of above

9.

Which one is having highest strength level ?

strong1

supply1

large1

pull1

10.

The Non-Blocking Procedural Assignment

The non-blocking procedural assignment allows you to schedule assignments without blocking the procedural flow

Syntax is <=

The simulator evaluates the right-hand side and schedules the assignment of the new value to take place at a time specified by a procedural timing control.

All of above

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