Verilog code for Asynchronous and Synchronous Reset Flip-Flop

There are both advantages and disadvantages to using either synchronous or asynchronous resets. The designer must use an approach that is appropriate for the design. Synchronous resets are based on the premise that the reset signal will only affect or reset the state of the flip-flop on the active edge of a clock.

Below is the basic diagram for Flip Flop.

Verilog Code for Asynchronous Reset FF. 

//--------------------------------------------------

//--------------------------------------------------

module  D_FF ( 

input clk, 

input rstn,

input d_in, 

output q_out 

);

always @(posedge clk or negedge rstn)  begin 

 if(!rstn)

  q_out <= 1'b0;

else 

 q_out <= d_in; 

end 

endmodule 

//--------------------------------------------------

//--------------------------------------------------

RTL code Synchronous Reset flip flop 

module  D_FF ( 

input clk, 

input rstn,

input d_in, 

output q_out 

);

always @(posedge clk)  begin 

 if(!rstn)

  q_out <= 1'b0;

else 

 q_out <= d_in; 

end 

endmodule 

//--------------------------------------------------

//--------------------------------------------------

Table of Contents