I²C (Inter-Integrated Circuit)

Transmitter   ->  This is the device that transmits data to the bus
Receiver         ->  This is the device that receives data from the bus
Multi-master  -> I2C can have more than one master and each can send commands
Synchronization -> A process to synchronize clocks of two or more devices

Slave               ->  This is the device that listens to the bus and is addressed by the master

Master            ->  This is the device that generates clock, starts communication, sends I2C commands and stops communication

Arbitration      -> A process to determine which of the masters on the bus can use it when more masters need to use the bus

Interface

It worked on 2 wire , SCL and SDA. 

Master is responsible for START and STOP condition. 

Serial Data Transfer
For each clock pulse one bit of data is transferred. The SDA signal can only change when the SCL signal is low – when the clock is high the data should be stable.

Modes

Standard mode  : 100 kbit/s

Full speed         :  400 kbit/s

Fast mode         :  1 mbit/s 

High speed        : 3,2 Mbit/s

Applicability of I2C protocol features 

Byte Format 

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

7-bit Addressing Format 

10-bit Addressing Format 

Details on ACK and NACK

ACK ->

The Acknowledge signal is defined as follows: the transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

Conditions which lead to NACK -> 

1.No receiver is present on the bus with the transmitted address so there is no device to respond with an acknowledge. 

2. The receiver is unable to receive or transmit because it is performing some real-time function and is not ready to start communication with the master. 

3. During the transfer, the receiver gets data or commands that it does not understand. 

4. During the transfer, the receiver cannot receive any more data bytes. 

5. A master-receiver must signal the end of the transfer to the slave transmitter.

Clock stretching 

Clock stretching pauses a transaction by holding the SCL line LOW. The transaction cannot continue until the line is released HIGH again. 

Clock stretching is optional and in fact, most slave devices do not include an SCL driver so they are unable to stretch the clock. On the byte level, a device may be able to receive bytes of data at a fast rate, but needs more time to store a received byte or prepare another byte to be transmitted. Slaves can then hold the SCL line LOW after reception and acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure. On the bit level, a device such as a microcontroller with or without limited hardware for the I 2C-bus, can slow down the bus clock by extending each clock LOW period. 

The speed of any master is adapted to the internal operating rate of this device. In Hs-mode, this handshake feature can only be used on byte level,

I2C Interview questions 

Q1. How can I generate a repeated start condition?

Let's assume the following situation: The controller lets the SCL line go high and the device pulls SDA low to acknowledge. So far no problem but how do you generate a repeated start condition now? The device is pulling SDA low.

First you have to complete the ACK cycle. To do this, you must pull SCL low again. The slave will release the data line when it detects that SCL is low. Now you can issue a stop command. To do this, you let the SCL go high again and then pull low the SDA line.

This is the confusing part of the procedure. Normally, you would suspect that by letting the clock line go high again you will be clocking in the first bit of a new byte. As a matter of fact that is the case. But since the chip will detect a START condition, this operation gets cancelled

Q2. Can I abort an ongoing I2C bus transmission?
Is it okay to abort an on-going transmission any time.

According to the specification, this should work. It depends on the layout of the component. A real I2C compatible IC will be able to handle this. It might make sense to test this before you use it.

Usually, when a START or STOP condition is detected, the internal logic of the chip is forced into a certain state. Internally, the logic that detects START and STOP is different from the logic that does all other processing. The START together with the address register is to be considered as a functional unit inside the chip.

When a START is detected, all internal operations are cancelled and the chip will compare the incoming data with its own address.

When a STOP is detected, ALL chips on the bus will reset their internal logic to IDLE mode except for the START detector (this is also used to cut power consumption). Therefore, when a start condition is issued on the bus, the START detector will 'wake-up' the rest of the internal logic.

Q3. Do I need to generate an ACK in read mode on the last byte?
This is a somewhat puzzling question. Indeed this is a bit strange. Usually, if you have read the last byte in a chip and generate an ACK, the chip should do nothing anymore, so the bus should be clear for you to create a STOP condition. Apparently, there are some chips that start transmitting data again. One such chip is the PCF 8574 I/O expander.

Though not always desirable, this feature can come in handy. If you need to sample incoming data fast, then you just continue reading from the chip. This prevents that you lose 'arbitration' of the bus in a multi-master environment.

It also speeds things up. You don't have to address the chip over and over again so you save the time for START, Address, ACK and STOP stage for every next byte read. This can lead to a more than doubled transfer rate.


Q4. Why does the SCL line have to be bi-directional?
The clock line needs to be bi-directional when using a MULTI-MASTER protocol and when using the synchronization protocol.

When you are using only one Master then this is not required since the clock will always be generated by this device. If you run Multi-master then this changes. One master must be able to receive data from another master. At that time it must be able to receive clock information via the clock line also.
How can I monitor the I2C bus?

There are a few commercial I2C monitor / debuggers around that can do this.

There is another possibility to do this: By using the stand-alone I2C controller PCF8584 from Philips. This chip has a certain mode in which it does not take part in the real I2C action but only records what is going on. It listens to all addresses, but does not generate any acknowledge. Using some software routines and a MCU you could build a universal I2C data logger.

Q5.How can I test / debug the I2C bus?

There is no general way to debug an I2C bus. However, a few guidelines might help to get it running.

First thing is to check the levels on the bus. You should see a clear signal that has a low level that is lower then 0.8 volt and a high level which is at least 3.5 volts.

If the high level is not high enough or does not rise fast enough then you can try to lower the value of the pull up resistor. You must take care however not to surpass the maximum allowable current in the I2C driver stage. The minimum allowable resistor for a 5 volt driven I2C bus is 5 V / 3mA = 1600 Ohms. A typical value of 4700 ohm should work fine.

Make sure the bus is not 'stuck' to '0'. This could be the result of a bad power supply (chips go into latch up during power-on) or a bad chip.

There are a few commercial I2C monitor / debuggers around.
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REF - http://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus/frequently-asked-questions/i2c-faq.html
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I2C
1. Can devices be added and removed while the system is running (Hot swapping) in I2C ? ( What is hot swapping in I2C ? )
a practical example is HDMI, which has some high speed IO for the video/sound, and then has I2C for control. If you were designing a monitor, or a video out device, you would need to support the plugging in of one or more monitors.

Hot swap can have issues with master reads in that the master will be ack-ing the read data bytes. If a slave is disconnected during a read, the master will see all 1's for the data bits. Some devices will include a checksum (ideally one where all 1's is not a valid choice) which helps to solve that corner-case.

I2C devices are addressed. If a device is hot swapped with one having the same address, there could be issues. If the master polls devices regularly, then it would be able to detect normal unplug/pluge events. Likewise, some circuits might provide an interupt to the uC for the connect plugged/unplugged.

2. What is the standard bus speed in I2C ?

3. How many devices can be connected in a standard I2C communication ?

4. What are the 2 roles of nodes in I2C communication ?

5. What are the modes of operation in I2C communication ?

6. What is bus arbitration ?

7. Advantages and limitations of I2C communication ?

8. How many wires are required for I2C communication ? What are the signals involved in I2C ?

9. What is START bit and STOP bit ?

10. How will the master indicate that it is either address / data ? How will it intimate to the slave that it is going to either read / write ?

11. Is it possible to have multiple masters in I2C ?

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