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Dec 28, 2016

Verilog Code for Round Robin Algorithm


Round Robin algorithm details :
Round Robin algorithm Verilog code :

What is Round Robin algorithm ?

Round-robin (RR) is one of the algorithms employed by process and network schedulers in computing.As the term is generally used, time slices (also known as time quanta) are assigned to each process in equal portions and in circular order, handling all processes without priority (also known as cyclic executive). Round-robin scheduling is simple, easy to implement, and starvation-free. Round-robin scheduling can also be applied to other scheduling problems, such as data packet scheduling in computer networks. It is an operating system concept.



Below is the diagram.




In the real situation, we can have a modified version of round robin.
Below feature can be include while designing a arbiter using round robin.
  1. If there are no requests,  which ever device/master send request, access will be given in next clock cycle.
  2. For some master, priority can be set. 
  3. Programmable delay to get the access if request is present. 

Below is the block diagram for round robin algorithm with 4 request and 4 grant.




Counter will be controlled by a state machine.




Verilog Code for Round Robin Algorithm



Below are the simulation results




In the same way, request/grant can be increased to n number.

Ref - https://en.wikipedia.org/wiki/Round-robin_scheduling

5 comments:

  1. can u mail me the code?
    mail id-shaikreshma06061998@gmail.com

    ReplyDelete
  2. Dear Sir,

    From lines 56 to 63 in the code, we are driving grnt_o based on the current req_i value.

    Again from lines 70 to 96, we are driving grnt_o based on both ring_cnt & req_i which is desirable.

    Please explain why do we need the first block of code despite the second block with ring_cnt serving the purpose.

    ReplyDelete
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    ReplyDelete
  4. How to change this code into CPP ? Can someone help pls ?

    ReplyDelete