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Nov 17, 2016

Verilog Code for FIR Filter


FIR filters are is widely used in different applications such as biomedical, communication and control due to its easily implementation, stability and best performance. Its simplicity makes it attractive for many applications where it is need to minimize computational requirements.

Below is the code for FIR Filter , Any comments/doubts are welcome.

Please contact me if you want a soft copy of the module.

Block diagram :


F is the flopped stage and C1/C2/C3/C4/C5  are the coefficient. One bug adder will required to add all the feedback.

Below is the verilog code for FIR filter with test bench.
-----------

module fir_filter (  a, b, clk, rstn) ;

input signed [31:0] a;
output signed [31:0] b;
input clk;
input rstn;


parameter avg = 20;
parameter  c1 = avg*(8'h1) ;
parameter  c2 = avg*(8'h1) ;
parameter  c3 = avg*(8'h1) ;
parameter  c4 = avg*(8'h1) ;
parameter  c5 = avg*(8'h1) ;


reg signed [31:0] f1 ;
reg signed [31:0] f2 ;
reg signed [31:0] f3 ;
reg signed [31:0] f4 ;
reg signed [31:0] f5 ;


always @(posedge clk or negedge rstn) begin
  if(!rstn)  begin
    f1 <= 32'b0;
    f2 <= 32'b0;
    f3 <= 32'b0;
    f4 <= 32'b0;
    f5 <= 32'b0;
  end
  else begin
    f1 <= a;
    f2 <= f1;
    f3 <= f2;
    f4 <= f3;
    f5 <= f4;
  end
end


assign b = (f1*c1 + f2*c2 + f3*c3 + f4*c4 + f5*c5)/(5*avg) ;


endmodule

module tb_fir;

reg [31:0] in_signal;
reg clk =0;
reg rstn =0;
reg en =0;
wire [31:0] out_signal;

always #5 clk = ~clk;

integer cnt=0;

always @(clk) cnt = cnt +1 ;

always @(*) begin
   if(en ==1 && cnt[2:0] == 3'b111) begin
   #1;
  in_signal = cnt[7:0];
  end
  end

fir_filter dut (
.a(in_signal),
.b(out_signal),
.clk(clk),
.rstn(rstn));

initial begin
  rstn =0 ;
  #100;
  rstn = 1;
  en =1;
  #10000 ;
  $finish;
end

initial
 $monitor("Input signal = %d , out_signal = %d", in_signal, out_signal);

initial begin
  $recordfile("test.trn");
  $recordvars();
  end

endmodule

------------------------- verilog code end -------------------- 

Downloads the verilog file here. 

8 comments:

  1. I want Verilog code for 16 tap FIR filter

    ReplyDelete
    Replies
    1. I can only help you to write the code.

      Delete
    2. Please write the code for 8 tap fir filter

      Delete
  2. sir I want fft verilog code,please can you provide for me??

    ReplyDelete
  3. How do i approach writing the code? I am trying to attempt write 64 point parallel fir

    ReplyDelete
  4. Hi i am new to this so please help to understand , we did not specify any cut off value or a range that should be passed through the filter then how will the unwanted signal that i want to remove will be removed ?? What if a part of my signal get removed i am confused

    ReplyDelete
  5. Hi i am new to this so please help to understand , we did not specify any cut off value or a range that should be passed through the filter then how will the unwanted signal that i want to remove will be removed ?? What if a part of my signal get removed i am confused

    ReplyDelete
  6. Hi how do I design for n-tap fir filter?

    ReplyDelete