Binary to 7-segment LED display is very easy , it is more like the decoding logic.
Below is the rtl code in Verilog for the same.
7 -Segment Display ->
Binary 7-segment
0000 a b c d e f g => 1 1 1 1 1 1 0
0001 a b c d e f g => 0 1 1 0 0 0 0
0010 a b c d e f g => 1 1 0 1 1 0 1
0011 a b c d e f g => 1 1 1 1 0 0 1
0100 a b c d e f g => 0 1 1 0 0 1 1
0101 a b c d e f g => 1 0 1 1 0 1 1
0110 a b c d e f g => 1 0 1 1 1 1 1
0111 a b c d e f g => 1 1 1 0 0 0 0
1000 a b c d e f g => 1 1 1 1 1 1 1
1001 a b c d e f g => 1 1 1 1 0 1 1
Below is the RTL code for the 7-segment LED Display.
// ---- RTL Code
module led_7_segment_dis (
input [3:0] bin_data,
output reg [6:0] led_7seg
);
always @(*) begin
led_7seg = 7'b0;
case(bin_data) // abcdefg
4'h0: led_7seg = 7'b1111110;
4'h1: led_7seg = 7'b0110000;
4'h2: led_7seg = 7'b1101101;
4'h3: led_7seg = 7'b1111001;
4'h4: led_7seg = 7'b0110011;
4'h5: led_7seg = 7'b1011011;
4'h6: led_7seg = 7'b1011111;
4'h7: led_7seg = 7'b1110000;
4'h8: led_7seg = 7'b1111111;
4'h9: led_7seg = 7'b1111011;
default : led_7seg = 7'b0;
endcase
end
always @(*) begin
$display("Binary number = %d", bin_data);
end
always @(*) begin
#1;
if(led_7seg[6])
$display(" ------");
if(led_7seg[5] && led_7seg[1]) begin
$display(" | |");
$display(" | |");
end
else if(led_7seg[5]) begin
$display(" |");
$display(" |");
end
else if(led_7seg[1]) begin
$display(" | ");
$display(" | ");
end
if(led_7seg[0])
$display(" ------");
if(led_7seg[4] && led_7seg[2]) begin
$display(" | |");
$display(" | |");
end
else if(led_7seg[4]) begin
$display(" |");
$display(" |");
end
else if(led_7seg[2]) begin
$display(" | ");
$display(" | ");
end
if(led_7seg[3])
$display(" ------");
end
endmodule
module tb;
reg [3:0] cnt =0;
always #5 cnt = cnt +1 ;
led_7_segment_dis dut(
.bin_data(cnt)
);
initial begin
#1000 ;
$finish;
end
endmodule
The way you modeled the digit is nice..though it's not 7 segmented!
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