Low Power Design Technique : Tutorials

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Here are some low power technique used during RTL .

There are 3 main components for power calculation.

1. Dynamic Power
2. Static Power
3. Short Circuit Power 

Dynamic power 

Dynamic power of a chip can be reduced by reducing the number of switching from 1's to 0's and vice versa, this is design change and will required some of the best practice to write the HDL code. Few of them are listed below.

• Writing RTL for low power design

Static power 

Static power can be controlled by below techniques.

Multi voltage in design or it is called voltage island : 

multi voltage design in vlsi :

For Multi VDD See the UPF example , how the UPF is getting define for multi voltage design. Below is one of the simple example. Any communication from voltage1 to voltage2 will have to go through the level shifter to avoid any timing issues. 

How to insert Lever shifter for Voltage cross domain -> See UPF Example
Reducing voltage will reduce the power consumption but it will also reduce the performance of the block , it means if a block is expected to run at high frequency, there could be timing issues if using low voltage. Remember with higher voltage , setup time will be less. This is effective in SoC where a block is not expected to run at higher frequency. 

Synthesis setup would be different for multi voltage design , 1st UPF should be align with the voltage island. Level shifters libraries has to include in synthesis setup.

DVFS (dynamic voltage frequency scaling)

Dynamic voltage and frequency scaling (DVFS) is a technique that aims at reducing the dynamic power consumption by dynamically adjusting voltage and frequency of a CPU. This technique exploits the fact that CPUs have discrete frequency and voltage settings as previously described.

DVFS techniques provide effective power saving by reducing the voltage on the fly based on the performance requirements , it also reduce the operating frequency. This is the only techniques which is highly effective on dynamic and static power saving. Reducing frequency will reduce the dynamic power where as reducing voltage will reduce the static power. 

DVFS Example:

Implementation of  Dynamic Voltage Frequency Scaling : 

In the implementation stage , DVFS is done by using a combination of MSV and MMMC ( multi-mode/multi-corner) techniques. 

Multi Voltage Threshold

Multi Vth  is using multi voltage threshold level in the design , they are known as LVT/SVT/HVT cells and there utilization is depends on the timing requirement. LVT is faster cell but they have more leakage hence static power consumption will be more. 

A quick info on LVT/HVT cells.

Power gating Technique

(power shut off) -> This will require UPF to implement power switches in the design. We use power switch where some part of the design is not required to be active all the time.

Physical Implementation of Power Gating :

Synthesis uses the power switches according to the definition in UPF ( power swtich must be define in UPF , it describe the control signal and other details which is required for synthesis tool to implement it.  The main task during synthesis is adding isolation cells, retention cells and always on cells define in UPF. The conneciton of power switch cells to the power control module happens during the physical implementation flow, when physical implementation information is available to the tool. 

Clock Gating Circuit 

Most of the dynamic power in design is consumed by clock , clock gating is the effective way to reduce the power consumption. There are options available in synthesis tool where you can enable the auto clock gating option , Tool will insert the clock gating at most of the places.

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Table of Contents


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multi voltage design in vlsi

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SPI Protocol