Low Power Design : Level Shifter

 
Level Shifter for Low Power Design. : 
Low Power Design Level Shifter : 

Low-Power Design: Level Shifters

A level shifter is a circuit used in low-power digital design to safely transfer signals between blocks operating at different voltage levels (VDDs). They are critical in multi-voltage (multi-VDD) / power-gated designs.

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Why level shifters are needed

Without level shifters:

• Over-voltage stress can damage transistors

• Logic ‘1’ may not be recognized correctly

• Leakage current can flow from high-VDD to low-VDD domains

• Power-gated blocks can back-power other domains

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Typical low-power SoC scenario

Block Supply

Always-ON (AON) 1.0 V

Logic core 0.8 V

High-performance 1.2 V

Signals crossing these domains must use level shifters.

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Types of level shifters

1️⃣ Low-to-High (Up-Shifter)

• Converts lower voltage logic to higher voltage

• Most common

• Usually cross-coupled PMOS structure

Example:

0.8 V → 1.2 V

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2️⃣ High-to-Low (Down-Shifter)

• Converts higher voltage logic to lower voltage

• Often simpler

• Sometimes just a buffer (but leakage must be controlled)

Example:

1.2 V → 0.8 V

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3️⃣ Bidirectional Level Shifter

• Used in buses (I²C, GPIO)

• Direction controlled dynamically

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Where level shifters are placed

Situation Placement

Signal enters higher-VDD domain At receiver side

Signal enters lower-VDD domain At sender side

Power-gated block Before isolation or after isolation (depends on policy)

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Low-Power Design Considerations

🔋 1. Leakage Power

• Level shifters can leak if always powered

• Use:

• High-Vt devices

• Power-gated level shifters

• Retention-aware designs

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⚡ 2. Dynamic Power

Dynamic power ∝ C × V² × f

Up-shifters increase:

• Load capacitance

• Switching energy (higher VDD)

➡️ Minimize number of crossings

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🛑 3. Interaction with Power Gating

Case: Signal from OFF domain → ON domain

Problem:

• Floating / X values

Solution:

• Isolation cells before level shifters

OFF domain → Isolation → Level Shifter → ON domain

Case: Signal from ON domain → OFF domain

• Level shifter must be in always-on domain

• Otherwise output may collapse

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🧱 4. Always-ON Requirement

Some level shifters must remain powered:

• Reset

• Wake-up signals

• Handshake signals

These are placed in AON power domain.

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Level Shifters vs Isolation Cells

Feature Level Shifter Isolation Cell

Voltage conversion ✅ Yes ❌ No

Blocks leakage ❌ No ✅ Yes

Prevents X-propagation ❌ ✅

Used across power domains ✅ ✅

👉 Often both are required.

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Example (conceptual RTL – tool inserts cells)

// Designer intent (no explicit level shifter)

assign data_to_high = data_from_low;

Actual implementation (by synthesis + UPF)

LOW_VDD → Level Shifter → HIGH_VDD

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UPF (Unified Power Format) intent example

create_power_domain PD_LOW

create_power_domain PD_HIGH

set_level_shifter LS_L2H \

   -from PD_LOW \

   -to PD_HIGH \

   -location to

EDA tools automatically:

• Insert correct LS cells

• Choose L2H or H2L

• Handle placement & connectivity

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Common interview questions

Q: Why are level shifters power-hungry?

➡️ Because they drive signals at higher VDD and add extra capacitance.

Q: Can isolation replace level shifters?

➡️ No. Isolation does not change voltage levels.

Q: What happens if level shifter is placed in switched-off domain?

➡️ Output collapses → functional failure.

Summary

• Level shifters are mandatory in multi-VDD low-power designs

• Critical for signal integrity, leakage control, and reliability

• Correct placement & power intent (UPF) is essential

Interview questions on level shifter : 

Here are more interview + concept-checking questions on Level Shifters, moving from basic → advanced → real-silicon / debug level, focused on low-power VLSI / SoC design.

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🔹 Basic Concept Questions

1. What is a level shifter and why is it required in low-power design?

2. Can a buffer replace a level shifter? When and why?

3. What happens if a signal from a low-VDD domain directly drives a high-VDD flop?

4. Why are level shifters not required within a single voltage domain?

5. Difference between L2H and H2L level shifters?

6. Why do up-shifters consume more power than down-shifters?

7. Are level shifters combinational or sequential?

8. Can level shifters introduce delay? Why?

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🔹 Placement & Power Domain Questions

9. Where should a level shifter be placed: source domain or destination domain? Why?

10. What happens if a level shifter is placed in a power-gated (switched-off) domain?

11. Why are some level shifters placed in the Always-ON (AON) domain?

12. Can level shifters be power-gated?

13. What is back-powering, and how do level shifters prevent it?

14. Do all signals crossing power domains need level shifters?

15. What happens if voltage difference between domains is very small?

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🔹 Level Shifter vs Isolation

16. Difference between level shifter and isolation cell?

17. Why is isolation often needed along with level shifters?

18. Order question:

Isolation → Level Shifter OR Level Shifter → Isolation?

Explain with OFF → ON case.

19. Can an isolation cell do voltage conversion?

20. What kind of bugs occur if isolation is missing but level shifter is present?

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🔹 Timing & STA Questions

21. How are level shifters treated in STA?

22. Do level shifters affect setup and hold timing?

23. Can level shifters cause hold violations? Why?

24. Are level shifters considered part of clock path or data path?

25. How does voltage scaling impact level shifter delay?

26. Why do level shifters need special timing libraries?

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🔹 UPF / CPF / Tool Flow Questions

27. Do designers instantiate level shifters in RTL?

28. How does UPF help in level shifter insertion?

29. Explain this UPF command:

set_level_shifter -from PD1 -to PD2 -location to

30. What does -location to mean?

31. What happens if level shifter rules are missing in UPF?

32. Can tools insert wrong type of level shifter? When?

33. How do tools decide between L2H and H2L?

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🔹 Clock & Reset Related Questions

34. Can clocks pass through level shifters?

35. Why is clock level shifting risky?

36. How are gated clocks handled across voltage domains?

37. Should reset signals use level shifters?

38. What happens if async reset comes from a higher-VDD domain?

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🔹 Advanced / Silicon-Level Questions

39. What is contention current in level shifters?

40. Why cross-coupled PMOS are used in up-shifters?

41. What causes metastability in level shifters?

42. How does temperature affect level shifter behavior?

43. Why are level shifters hotspots for IR drop?

44. What is crowbar current in level shifters?

45. How do you reduce leakage in always-on level shifters?

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🔹 Debug & Failure Scenarios (Very Important)

46. Chip works at typical corner but fails at low voltage – role of level shifters?

47. Simulation is clean but silicon fails – what LS issues to suspect?

48. X-propagation seen after power-up – LS or isolation issue?

49. Scan chain broken – could level shifter be the reason?

50. Why do wake-up signals fail if LS is wrongly powered?

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🔹 Short Answer (Rapid-Fire)

51. Can level shifters latch data?

52. Do level shifters support bidirectional signals?

53. Are level shifters technology dependent?

54. Do they exist in standard cell libraries?

55. Can level shifters be shared across multiple signals?

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🔹 One-Line Concept Checks (Interview Gold)

56. “Isolation blocks values; level shifter changes voltage” – explain.

57. Why LS must be powered even when logic is OFF?

58. Why LS insertion increases congestion?

59. Why multi-bit LS cells are preferred?

60. Why LS are avoided on high-frequency paths?

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🔹 Case-Study Question

61.

A signal goes from 0.7 V domain (power-gated) to 1.0 V always-on domain.

• What cells are needed?

• Where should they be placed?

• What happens during OFF state?

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Quiz on UPF - MCQ 

Retention Cells - UPF/ Low_power_mode

RETENTION CELLS - UPF - Low Power

FIG-1

Retention Cell Details :

These cells are special flops with multiple power supply. 

They are typically used as a shadow register to retain their value even if the block in which they are residing, is shut down.

FIG-1 is simple diagram of retention cells.

Types of Retention cells : 

1) Master/slave-alive retention: 

In a master/slave-alive retention register, the retained value is held in the master or slave latch. In this case, the retention element is in the functional data-path of the register.

2) Balloon-style retention: 

In a balloon-style retention register, the retained value is held in an additional latch, often called the  balloon latch. In this case, the balloon element is not in the functional data-path of the register.

Ballon-style retention can be Dual-Pin Retention cell or Single-Pin Retention cell.
Master/slave-alive retention is same as Zero-Pin Retention cell.


3) Dual-Pin Retention :
Dual-Pin Retention is the one which has two separate control signal for save and restore operation.
Save operation can be level-sensitive or edge-sensitive.

4) Single-Pin Retention:
Single-Pin Retention is the one which has single control signal for both save and restore operation.
Save operation can be level-sensitive or edge-sensitive.
Save operation and Restore operation will be on opposite level/edge of control signal. i.e If save is performed on level high than restore will be performed on level low of control signal.


Zero-Pin Retention:
Zero-Pin Retention is the one which does not have any control signal .
Save operation will be performed when the power domain in which cell is sitting goes from NORMAL to CORRUPT state.

Restore operation will be performed when the power domain in which cell is sitting goes from CORRUPT to NORMAL state.

UPF syntax to define Retention cells in a design:

set_retention 

  retention_strategy 

  -domain power_domain 

 [-retention_power_net retention_power_net] 

 [-retention_ground_net retention_ground_net] 

 [-retention_supply retention_supply_set] 

 [-no_retention] 

 [-elements objects] 

 [-exclude_elements exclude_objects] 

 [-save_signal {save_signal save_sense}] 

 [-restore_signal {restore_signal restore_sense}] 

 [-save_condition {boolean_function}] 

 [-restore_condition {boolean_function}] 

 [-retention_condition {boolean_function}] [-update] 

 [-use_retention_as_primary]


retention_strategy is name of retention strategy.

retention_power/grounds are retention power supply.

elements are the registers/cells/design hier which you want to put under retention.

Below is the retention circuit timing diagram. 

Do not confuse between isolation cells and retention cells, isolation cells are to drive a known value when circuit goes into power saving mode while retention cells retain the last value and drive the same when normal power is back.

One of the example is shown below. 

set_retention  dummy1_retention -domain VDD \

                 -retention_supply_set VDD_DPSLP \

                 -retention_condition { /DUT/design/signal1 } \

                 -elements {  reg1*

                                     reg2*

                                   }

map_retention_cell dummy1_retention \

  -domain VDD -lib_cells  CELL1 

This is one of the simple example to define the retention strategy. 

Labels:

Understanding of Retention cells
Understanding Low power checks
Special cells used for power planning.

Low Power Design Technique : Tutorials

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Here are some low power technique used during RTL .

There are 3 main components for power calculation.

1. Dynamic Power
2. Static Power
3. Short Circuit Power 

Dynamic power 

Dynamic power of a chip can be reduced by reducing the number of switching from 1's to 0's and vice versa, this is design change and will required some of the best practice to write the HDL code. Few of them are listed below.

• Writing RTL for low power design

Static power 

Static power can be controlled by below techniques.

Multi voltage in design or it is called voltage island : 

multi voltage design in vlsi :

For Multi VDD See the UPF example , how the UPF is getting define for multi voltage design. Below is one of the simple example. Any communication from voltage1 to voltage2 will have to go through the level shifter to avoid any timing issues. 

How to insert Lever shifter for Voltage cross domain -> See UPF Example
Reducing voltage will reduce the power consumption but it will also reduce the performance of the block , it means if a block is expected to run at high frequency, there could be timing issues if using low voltage. Remember with higher voltage , setup time will be less. This is effective in SoC where a block is not expected to run at higher frequency. 

Synthesis setup would be different for multi voltage design , 1st UPF should be align with the voltage island. Level shifters libraries has to include in synthesis setup.

DVFS (dynamic voltage frequency scaling)

Dynamic voltage and frequency scaling (DVFS) is a technique that aims at reducing the dynamic power consumption by dynamically adjusting voltage and frequency of a CPU. This technique exploits the fact that CPUs have discrete frequency and voltage settings as previously described.

DVFS techniques provide effective power saving by reducing the voltage on the fly based on the performance requirements , it also reduce the operating frequency. This is the only techniques which is highly effective on dynamic and static power saving. Reducing frequency will reduce the dynamic power where as reducing voltage will reduce the static power. 

DVFS Example:

Implementation of  Dynamic Voltage Frequency Scaling : 

In the implementation stage , DVFS is done by using a combination of MSV and MMMC ( multi-mode/multi-corner) techniques. 

Multi Voltage Threshold

Multi Vth  is using multi voltage threshold level in the design , they are known as LVT/SVT/HVT cells and there utilization is depends on the timing requirement. LVT is faster cell but they have more leakage hence static power consumption will be more. 

A quick info on LVT/HVT cells.

Power gating Technique

(power shut off) -> This will require UPF to implement power switches in the design. We use power switch where some part of the design is not required to be active all the time.

Physical Implementation of Power Gating :

Synthesis uses the power switches according to the definition in UPF ( power swtich must be define in UPF , it describe the control signal and other details which is required for synthesis tool to implement it.  The main task during synthesis is adding isolation cells, retention cells and always on cells define in UPF. The conneciton of power switch cells to the power control module happens during the physical implementation flow, when physical implementation information is available to the tool. 

Clock Gating Circuit 

Most of the dynamic power in design is consumed by clock , clock gating is the effective way to reduce the power consumption. There are options available in synthesis tool where you can enable the auto clock gating option , Tool will insert the clock gating at most of the places.

Visit here to see more detail information on Low Power Design Techniques.

Table of Contents


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multi voltage design in vlsi

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SPI Protocol

RTL Techniques to make device a Low Power Device

In my last blog , I have explain about the low power technique which includes rtl modification , cell selection, using UPF file, power saving at physical level , etc . During RTL implementation, a good designer can save a significant amount of power.

As we all knows power loss in chip is due to static power and dynamic power. During RTL implementation, we can not do anything on static power but we can save dynamic power by reducing number of transitions at gates. Below are few bullet points.

Power Saving during RTL Implementation 

1. One should write RTL in such  way where transition should be minimum , for example

always@(posedge clk or negedge reset) begin
 if(reset)
    data_out <= 64'd0;
 else if (latch_en)
   data_out <= data_in;
 else
   data_out <= 64'd0 ;
end

Above code can be written as shown below -

always@(posedge clk or negedge reset) begin
 if(reset)
    data_out <= 64'd0;
 else if (latch_en)
   data_out <= data_in;
end

If there is no need to reset data_out when latch_en is not high , then there is no harm to leave previous data on data bus, this will save lot of transition and will result in saving power.

2.  Implement clock gating for the blocks which are not required in some power state or in functional mode.
Clock gating is important if design intention is low power , one using clock gating, should use proper clock gating cells. Enable/disable signal of clock gating should be synchronized with respective clock domain to avoid glitches.

3.  In a design, there may be lot of counters , big or small ... to save power , those counters should not be free running counters. Use start and stop condition and run those counters whenever required.
Counters should be taken care in micro-architecture document, start/stop condition will be depend on certain condition which should be met.

4. Sharing logic will also help in reducing power as well as effective gate count.
Logic may get optimized during synthesis as tool is now having intelligence to detect same kind of logic and optimized them. But this will open a small confusion window as tool may or may not optimized the logic. It is always advised to share logic at RTL stage itself.

5.  If design having big state machine then prefer to use gray coding or one hot coding , In binary coding , transition will be more and will consume more power.

When you are working on micro-architecture of design, and if you want to make design as low power design then you need to think carefully about the transition. sometimes it might be possible that transitions are not in big numbers but when you save small numbers transitions multiple places then it will result in saving good amount of power.

The only disadvantage is , hardware will be more as you need to implement more logic and consumption of your mind power will be more as you need to think out of box to implement the logic. But at the end you will be called "expert in Low Power Design" which will open a lot of opportunities for your career and your future.

Let me know if I am missing something here , I can add here and make this article more effective. 

Thanks for your time. 

Rahul Jain 

Low Power Design and Verification

Low power design is not a new area, but it was not that much important as it is now.
Semiconductor market trend is very fast changing , and it is a challenge to face and ready with new technology.

The low power design , these days it is important because technology is now getting saturated with 28 nm , if you go below of that then device will be more costlier. So now in coming days people will move into low power design, the other reason is , as you go from 160um to 28um,  power dissipation was not much on 90 or above um technology, but as technology moving into more advanced, power dissipation going higher and higher.

Other reason is , these days we are using battery operated device like cellphone, tablet, laptop, etc , one of the major factor on these device is battery , people want long life for battery  and a good low power design can give you long life battery

Below is the graph showing power trend with respect to time , as we are moving from 2006 to 2020, static power dissipation is more and more , static power dissipation happens when device is in idle state , which means , now a days there are many module which stay ideal most of time.

In CMOS , below is the chart for power consumption -

So .. Where does the power go ?

In SoC design , total power consists of dynamic power and static power.
Dynamic power dissipation is due to signal activity , when signal changing value from 1 to 0 or 0 to 1, there will be power dissipation.
Static power dissipation is due to leakage power and it happen when device is in ideal state.

Dynamic Power Dissipation

Below is the equation to calculate the dynamic power.

                           P(dyn)  =  C*Vdd*Vdd*f
where ..
f -  frequency
Vdd-  Voltage
C - effective capacitance

Dynamic Power depend on clock frequency , power supply , switching activity , transistor width ,length , etc

Static Power Dissipation 
Static power dissipation is due to leakage current. below is a pictorial comparison between dynamic power and static power.

There are few technique used to save power in design, few of them I have mentioned below.

Clock Gating

1. Clock trees are a large source of dynamic power.
2. Clock gating can occur at any level  in design. 
3. Try to put clock gating circuit near to clock source , this will save a significant amount of power. 

Operand Isolation

1. Datapath computation elements are sampled only periodically.
2. Adding one enable signal and control sampling with enable signal.
3. Whenever enable is inactive , datapath inputs can be forced to constant value, this will result in saving dynamic power.

Multi Vth

1. Multiple voltage threshold optimization utilizes gates with different threshold to optimize for power, timing and area constraint. 
2. A good synthesis tool should be able to mix available multi threshold library cells to meet speed and area constraint with low power dissipation.

MSV ( Multi Supply Voltage)

1. Multi-supply voltage techniques operate different blocks at different voltages.
2. Running at a lower voltage reduces power consumption, but at the expense of speed. 
3. Designers use different supply voltages for different parts of the chip based on their performance requirements.
4. MSV implementation is key to reducing power since lowering the voltage has a squared effect on active power consumption.
5. MSV techniques require level shifters on signals that go from one voltage level to another. 
6. Without level shifters, signals that cross voltage levels will not be sampled correctly.

Dynamic Voltage and frequency scaling 

Supply voltage plays a major role power dissipation as it used in calculation in dynamic power as well as leakage power dissipation. Reducing voltage supply will save a lot of power but it will make design work at lower frequency. If you reduced voltage , then this will result in increment of combinational/sequencial delays. Also if design is working at low frequency then power dissipation will be less. This is dynamic power management and may be hardware/firmware control power supply and frequency of design, depends on implementation.

Power Shut-Off  (PSO)

1. One of the most effective technique – called power gating.
2. Switch off the power to parts of chips when blocks are not in use.
3. it can eliminate up to 96% of leakage current.
4. A specific power sequence is needed which includes isolation on signals from the power down domain.

Isolation 

1. Isolation logic is typically used at the output of a powered-down block to prevent floating or unpowered signals from propagating from powered-down blocks.
2. The outputs of blocks being powered down need to be isolated before power can be switched off; and they need to remain isolated until after the block has been fully powered up. Isolation cells are placed between two power domains and are typically connected from domains powered off to domains that are still powered up.

State Retention 

1. To speed-up recovery, state retention power gating flops can be used. 
2. Those flops retain their state while the power is off. 
3. Area of verification is to checking the library specific requirement should be satisfied and flops actually retaining their state.

Memory Splitting

1. In many systems, the memory capacity is designed for peak usage. During normal system activity, only a portion of memory is actually used at any given time.
2. In many cases, it is possible to divide the memory into two or more sections and selectively power down unused section of memory.

Low Power Verification 

Low power verification is having extra effort in verification to verify low power design , there are few area which we can not verify in simulation but there are tools available in market. 

In simulation perspective, below features can be verified - 

1. Power up/Power down sequence 
2. Assertions on boundary 
3. Isolation/Retention cells verification
4. Hardware-Software deadlock 
5. Power-on Reset/ Bring up

UPF (Unified Power Format)  - 

UPF plays a major role in low power design , this is a TCL based script which having information about the power intent of design and specify the power domain.  This file is similar to SDC file , except SDC has timing information and UPF has power related information but syntax totally different in SDC and UPF.  If there are multi supply voltage used in design, then designer will have to create UPF file and put that information into file.

Few points about UPF -

1. IEEE 1801 standard format
2. Extension of Tcl tool command language 
3. Defined separately from HDL
4. Enables early verification 
5. Drive verification and implementation from RTL to layout 

Common command used in UPF 

• create_power_domain
• set_isolation
• set_level_shifter
• set_retention
• create_supply_port
• create_supply_net
• create_power_switch
• connect_supply_net
• add_port_state
• create_pst
• add_ast_state .. etc 

For more detail on UPF , visit below page .. 

UPF (Unified Power Format)

Other Topics -
Contents
Refreshing your brain with Verilog 
Digital Design of Hybrid Memory Cube
Correct way of  Digital design RTL Coding
Clock Gating Circuits
Digital Design Interview Question
Knowledge on Verification
How To debug a simulation
Retention cells 

More are yet to come , all comments and suggestions are welcome and will help to put information here.  

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