Retention Cells - UPF/ Low_power_mode

RETENTION CELLS - UPF - Low Power

FIG-1

Retention Cell Details :

These cells are special flops with multiple power supply. 

They are typically used as a shadow register to retain their value even if the block in which they are residing, is shut down.

FIG-1 is simple diagram of retention cells.

Types of Retention cells : 

1) Master/slave-alive retention: 

In a master/slave-alive retention register, the retained value is held in the master or slave latch. In this case, the retention element is in the functional data-path of the register.

2) Balloon-style retention: 

In a balloon-style retention register, the retained value is held in an additional latch, often called the  balloon latch. In this case, the balloon element is not in the functional data-path of the register.

Ballon-style retention can be Dual-Pin Retention cell or Single-Pin Retention cell.
Master/slave-alive retention is same as Zero-Pin Retention cell.


3) Dual-Pin Retention :
Dual-Pin Retention is the one which has two separate control signal for save and restore operation.
Save operation can be level-sensitive or edge-sensitive.

4) Single-Pin Retention:
Single-Pin Retention is the one which has single control signal for both save and restore operation.
Save operation can be level-sensitive or edge-sensitive.
Save operation and Restore operation will be on opposite level/edge of control signal. i.e If save is performed on level high than restore will be performed on level low of control signal.


Zero-Pin Retention:
Zero-Pin Retention is the one which does not have any control signal .
Save operation will be performed when the power domain in which cell is sitting goes from NORMAL to CORRUPT state.

Restore operation will be performed when the power domain in which cell is sitting goes from CORRUPT to NORMAL state.

UPF syntax to define Retention cells in a design:

set_retention 

  retention_strategy 

  -domain power_domain 

 [-retention_power_net retention_power_net] 

 [-retention_ground_net retention_ground_net] 

 [-retention_supply retention_supply_set] 

 [-no_retention] 

 [-elements objects] 

 [-exclude_elements exclude_objects] 

 [-save_signal {save_signal save_sense}] 

 [-restore_signal {restore_signal restore_sense}] 

 [-save_condition {boolean_function}] 

 [-restore_condition {boolean_function}] 

 [-retention_condition {boolean_function}] [-update] 

 [-use_retention_as_primary]


retention_strategy is name of retention strategy.

retention_power/grounds are retention power supply.

elements are the registers/cells/design hier which you want to put under retention.

Below is the retention circuit timing diagram. 

Do not confuse between isolation cells and retention cells, isolation cells are to drive a known value when circuit goes into power saving mode while retention cells retain the last value and drive the same when normal power is back.

One of the example is shown below. 

set_retention  dummy1_retention -domain VDD \

                 -retention_supply_set VDD_DPSLP \

                 -retention_condition { /DUT/design/signal1 } \

                 -elements {  reg1*

                                     reg2*

                                   }

map_retention_cell dummy1_retention \

  -domain VDD -lib_cells  CELL1 

This is one of the simple example to define the retention strategy. 

Labels:

Understanding of Retention cells
Understanding Low power checks
Special cells used for power planning.

UPF Example

Below link is the UPF example, I have tried my best to put all things in one page to get better understanding.

You might have to adjust your display setting to view it properly.

This diagram does not included the advanced command of UPF (new commands added in UPF2.0 ) , I will try to get those command in same figure .. Keep visiting my blog for updates.

My linked-in profile -
Linked-in (Rahul Jain)

Other useful links -
How To debug a simulation 
Refreshing your brain with Verilog 
Digital Design of Hybrid Memory Cube
Correct way of  Digital design RTL Coding
Clock Gating Circuits
Digital Design Interview Question
Knowledge on Verification


Simulator Execution for Blocking and non-blocking statement 

(UPF) Unified Power Format

VLSI Digital Design Interview Questions  

Unified Power Format (UPF) is the popular name of the Institute of Electrical and Electronics Engineers (IEEE) standard for specifying power intent in power optimization of electronic design automation. The IEEE 1801-2009 release of the standard was based on a donation from the Accellera organization.

How does it started ? 

A technical committee was formed by the Accellera organization, chaired by Stephen Bailey (Mentor Graphics). This group was met on Sep13,2006 and it submitted its first draft in Jan 2007. After that Version 1.0 was approved to be published on Feb 26,2007, Joe Daniel was technical editor. 

After publishing version 1.0, there were 2 other version published later , version 2.0 and version 2.1. 

Accellera UPF in 2007 (1.0)

IEEE 1801-2009 UPF (2.0)

IEEE 1801-2013 UPF (2.1) 

Q. What is UPF and how to use it in design ? 

UPF is Tcl based syntax and semantics and can be mixed with non-UPF Tcl commands. I will explain the usage of this file. 

This file defining the power management architecture of the design, and used in generating customized reports related to power intent of design.There are standard commands defined in UPF which tool understand and respond according to that. 

UPF Flow 

Below is a snapshot of UPF 1.0 version commands, all commands will have explanation. 

Power Doamin
This is not a command but a term used while explaining the commands.
A power domain is a collection of design elements that share a primary power and ground supply net. The
logic hierarchy level where a power domain is created is called the scope of the power domain. Any design
elements that belong to a power domain are said to be in the extent of that power domain.
Whenever a UPF object, such as a supply net or switch is created, it is always created in the scope of the
power domain.

UPF commands 

set_scope
It specify the current scope of UPF , syntax is
set_scope my_dut/design_a

set_design_top

It specify the top level design instance , this information is used only by simulation and verification tools.
Syntax -
set_design_top <design name>

create_supply_port
Syntax of this command is -
create_supply_port  port_name -domain <domain_name> -direction <in | out >

create_supply_net 
The create_supply_net command creates a supply net. The net is defined for the power domain, created in the logic hierarchy at the same scope as domain_name, and propagated through implicitly created ports and nets through the logic hierarchy as required.
Syntax -
create_supply_net <net_name> -domain <power_domain> -reuse  -resolve <unresolved | parallel | one hot>

Here -domain is power domain where you want to create net.
-reuse - (optional) extend net_name as a supply net within domain_name , new nets will not be created.
-resolve  - optional

connect_supply_net
This command used to connect supply_net to supply ports or/and supply pins.
Syntax -
connect_supply_net net_name  [-ports list] [-pins list]  [<-cells list |-domain domain_name>]  [<-rail_connection rail_type | -pg_type pg_type>]* [-vct vct_name]

-cells list A list of cells to use for -rail_connection or -pg_type.
-domain domain_name The domain to use for -rail_connection or -pg_type.
-rail_connection rail_type  (The rail type (for older libraries).)
-pg_type pg_type The power/ground pin type.
-vct vct_name A VCT defining how values are mapped from UPF to an HDL model or from the HDL model to UPF.

create_power_switch

It define a power switch in the power domain.
Syntax -
create_power_switch switch_name
-domain domain_name
-output_supply_port {port_name supply_net_name}
{-input_supply_port {port_name supply_net_name}}
{-control_port {port_name net_name}}
{-on_state {state_name input_supply_port {boolean_function}}}
[-on_partial_state {state_name input_supply_port {boolean_function}}]
[-ack_port {port_name net_name [{boolean_function}]}]
[-ack_delay {port_name delay}]
[-off_state {state_name {boolean_function}}]
[-error_state {state_name {boolean_function}}]

create_power_domain
It define the power supply distribution network, a power domain is logical grouping of one or more design elements.

Syntax -
create_power_domain domain_name [-elements list]  [-include_scope]  [-scope instance_name]
domain_name - new power domain, should be a simple name
-element <list> , list is specified to current scope , not influenced by -scope argument
if -include_scope is specified , the scope of domain is included in the extent of the domain.
-scope , it specifies the scope i.e. where the domain shall be created.
Example -
create_power_domain PD1 -elements {top/U1}
set_scope /top/U1
create_power_domain PD2

set_domain_supply_net

Set default power and ground supply net for a power domain.
Syntax -
set_domain_supply_net domain_name   -primary_power_net supply_net_name  -primary_ground_net supply_net_name

add_port_state
Specify the name and value for a supply port.
Syntax -
add_port_state port_name  {-state {name <nom | <min nom max> | off>}}

Example -
add_port_state VPP  -state {active_state 0.88 0.90 0.92}   -state {off_state off}

create_pst
Create a power state table with a specific ordering of supply nets.
Syntax -
create_pst table_name  -supplies list

A power state table is used for implementation — specifically for synthesis, analysis, and optimization. It
defines the legal combinations of states, i.e., those combinations of states that can exist at the same time
during operation of the design.

add_pst_state

Define the states of each of the supply nets for one possible state of the design.
Syntax -
add_pst_state state_name  -pst table_name  -state supply_states

Syntax example:
create_pst pt -supplies { N1 N2 DUT/T1/VDD1 }
add_pst_state s0 –pst pt –state { s08 s08 s0 }
add_pst_state s1 –pst pt –state { s08 s08 off }
add_pst_state s2 –pst pt –state { s08 s09 off }

set_retention

Defining the retention registers in design.
Syntax -
set_retention retention_name -domain domain_name  <-retention_power_net net_name | - retention_ground_net net_name | -retention_power_net net_name -retention_ground_net net_name>  [-elements list]

set_retention_control
It specify the control signals and assertions for retention cells.
Syntax -
set_retention_control retention_name -domain domain_name  -save_signal {{net_name <high | low | posedge | negedge>}}  -restore_signal {{net_name <high | low | posedge | negedge>}}
[-assert_r_mutex {{net_name <high | low | posedge | negedge>}}]
[-assert_s_mutex {{net_name <high | low | posedge | negedge>}}]
[-assert_rs_mutex {{net_name <high | low | posedge | negedge>}}]

set_isolation
Specify the elements in the domain to isolate using the specified strategy.
set_isolation isolation_name -domain domain_name  <-isolation_power_net net_name | -isolation_ground_net net_name |  -isolation_power_net net_name -isolation_ground_net net_name | -no_isolation>  [-elements list] [-clamp_value <0 | 1 | latch | Z>] [-applies_to <inputs | outputs | both>]

set_isolation_control
Specify the isolation control signals and assertions in specified strategy.
Syntax -
set_isolation_control isolation_name  -domain domain_name  -isolation_signal signal_name  [-isolation_sense <high | low>]  [-location <self | parent | sibling | fanout | automatic>]

set_level_shifter

Specify the level shifter in design.
Syntax -
set_level_shifter level_shifter_name  -domain domain_name  [-elements list] [-applies_to <inputs | outputs | both>]  [-threshold value] [-rule <low_to_high | high_to_low | both>]  [-location <self | parent | sibling | fanout | automatic>] [-no_shift]

map_retention_cell
Specify the retention cells used for retention registers.
Syntax -
map_retention_cell retention_name
-domain domain_name
[-elements list]
[-lib_cells list]
[-lib_cell_type lib_cell_type]
[-lib_model_name lib_cell_name {-port port_name net_name}]

map_isolation_cell
Syntax -
map_isolation_cell isolation_name  -domain domain_name [-elements list]  [-lib_cells list]  [-lib_cell_type lib_cell_type]  [-lib_model_name lib_model_name {-port {port_name net_name}}]

map_level_shifter_cell
Map a particular level shifter strategy to a library cell or range of library cells.
Syntax -
map_level_shifter_cell level_shifter_name  -domain domain_name  -lib_cells list [-elements list]

map_power_switch_cell

Specify which power switch cell is to be used for the corresponding switch instance.
map_power_switch switch_name  -domain domain_name  -lib_cells list

bind_checker
Inserts checker modules and binds them to design elements.
Syntax -
bind_checker instance_name  -module checker_name  -elements list  [-ports {{port_name net_name}}]

create_hdl2upf_vct
Define value conversion table that can be used in converting HDL logic values into net_state_type values.
Syntax -
create_hdl2upf_vct vct_name  -hdl_type {<vhdl | vlog | SV> [typename]}  -table {{from_value to_value}}

create_upf2hdl_vct

Define value conversion table that can be used in converting UPF supply_net_type.state(1:0) values into HDL logic values.
Syntax -
create_upf2hdl vct_name  -hdl_type {<vhdl | vlog | SV> [typename]}  -table {{from_value to_value}}

upf_version
Specify the version for the UPF file/syntax.
Syntax -
upf_version [string]

load_upf
Set the scope to the specified instance and execute the specified UPF commands.
Syntax -
load_upf upf_file_name  [-scope instance_name]  [-version string]

save_upf

Create a UPF file relative to the specified scope.
Syntax -
save_upf upf_file_name  [-scope instance_name]  [-version string]

----------------------------------------------------------------------------------------------------------

After UPF version 1.0, there was in need of enhancement to save power more precisely, then UPF 2.0 came in 2009. In UPF2.0, there were many new commands , below is a summary of UPF2.0 addition.

Red commands are the new addition in UPF 2.0. 

set_simstate_behavior
Specify the simulation simstate behavior for a model or library.
Syntax-
set_simstate_behavior <ENABLE | DISABLE>  [-lib name]  [-model model_list]  [-elements element_list] [-exclude_elements exclude_list]

set_port_attributes
It defines attributes on ports.
Syntax -
set_port_attributes   [-model name]
[-elements element_list]
[-exclude_elements element_exclude_list]
[-ports port_list]
[-exclude_ports port_exclude_list]
[-applies_to <inputs | outputs | both>]
[-attribute {name value}]*
[-clamp_value <0 | 1 | any | Z | latch | value>]
[-sink_off_clamp <0 | 1 | any | Z | latch | value>]
[-source_off_clamp <0 | 1 | any | Z | latch | value>]
[-driver_supply supply_set_ref]
[-receiver_supply supply_set_ref]
[-pg_type pg_type_value]
[-related_power_port supply_port_name]
[-related_ground_port supply_port_name]
[-related_bias_ports supply_port_name_list]
[-feedthrough]
[-unconnected]
[{-domains domain_list [-applies_to <inputs | outputs | both>]}]
[{-exclude_domains domain_list [-applies_to <inputs | outputs | both>]}]
[-repeater_supply supply_set_ref]
[-transitive [<TRUE | FALSE>]]

set_design_attributes
Apply attributes to models or instances
Syntax -
set_design_attributes  [-models model_list]  [-elements element_list]  [-exclude_elements exclude_list]  [-attribute {name value}]  [-is_leaf_cell [<TRUE | FALSE>]]  [-is_macro_cell [<TRUE | FALSE>]]

associate_supply_set
Associate a supply set with a power domain, power switch, or strategy supply set handle.
Syntax -
associate_supply_set supply_set_name
-handle supply_set_handle

set_retention_elements 

Create a named list of elements to be used in set_retention or map_retention_cell commands
Syntax -
set_retention_elements retention_list_name  -elements element_list
[-applies_to <required | not_optional | not_required | optional>]
[-exclude_elements exclude_list]
[-retention_purpose <required | optional>]
[-transitive [<TRUE | FALSE>]]
[-expand [<TRUE | FALSE>]]

use_interface_cell

Specify the functional model and a list of implementation targets for isolation and level-shifting.
Syntax -
use_interface_cell interface_implementation_name  -strategy list_of_isolation_level_shifter_strategies
-domain domain_name  -lib_cells lib_cell_list
[-port_map {{port net_ref}*}]
[-elements element_list]
[-exclude_elements exclude_list]
[-applies_to_clamp <0 | 1 | any | Z | latch | value>]
[-update_any <0 | 1 | known | Z | latch | value>]
[-force_function]
[-inverter_supply_set list]

create_logic_port
Define a logic port.
Syntax -
create_logic_port port_name  [-direction <in | out | inout>]

create_logic_net
Define a logic net.
Syntax -
create_logic_net <net_name>

connect_logic_net
Connect a logic net to logic ports.
Syntax -
 connect_logic_net net_name  -ports port_list  [-reconnect]

load_upf_protected
Load a UPF file in a protected environment that prevents corruption of existing variables.
Syntax -
load_upf_protected upf_file_name  [-hide_globals] [-scope instance_name_list]  [-version upf_version] [-params param_list]

load_simstate_behavior
Load the simstate behavior defaults for a library.
Syntax -
load_simstate_behavior lib_name  -file file_list

find_objects

Find logic hierarchy objects within a scope.

create_composite_domain
A composite power domain is a simple container for a set of power domains. Unlike a power domain, a

composite domain has no corresponding physical region on the silicon.

add_power_state
Define power state(s) of a power domain or supply set.
Syntax -
add_power_state object_name  [-supply | -domain]  [-state {state_name [-supply_expr {boolean_expression}]  [-logic_expr {boolean_expression}]  [-simstate simstate] [-legal | -illegal]}] [-complete]  [-update]

describe_state_transition

Describe a state transition’s legality.
Syntax -
describe_state_transition transition_name  -object object_name  [-from from_list -to to_list]
[-paired {{from_state to_state}}]  [-legal | -illegal]

Each command will need a detail explanation, I have tried to put more information in below post.

UPF Example 

Ref-
http://en.wikipedia.org/wiki/Unified_Power_Format
ftp://c-76-121-39-184.hsd1.wa.comcast.net/AiDisk_a1/WK/FP/PROJ/docs/IEEE/1801-2013.pdf

Other Topics -
Contents
Refreshing your brain with Verilog 
Digital Design of Hybrid Memory Cube
Correct way of  Digital design RTL Coding
Clock Gating Circuits
Digital Design Interview Question
Knowledge on Verification

All comments and suggestions are welcome and will help me to put information here.  

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