Today in semiconductor industry, verification is more important than design. One can make design perfect but verification will decide whether design going to work or not. There are many ways to verify the design. Now a day, People are talking about random verification using ovm or uvm.
In my words, verification is some thing like generate stimulus for design and monitor the response. To built verification environment.. one has to be cleared about the IO's definition. If verification engineer knows what to drive and more important when to drive... she/he can create environment very well. I am putting some points which may help you to understand the verification environment.
1. IO's definition should be clear.
2. Make a block diagram, most of the design follow a protocol, if that is the case then think about to have BFM to cover that part of functionality.
3. Monitor can be placed anywhere in environment, but mostly monitor will sit at the interface of design and verification environment. Monitor could be a active entity or could be a passive entity..depends on the functionality.
4. Verification engineer should always be thinking of how to break the logic...?? Today's designer are very smart ,they also do the sanity verification before handing over the design to verification engineer. So verification team will have to create corner cases .
5. One way to break design is .....implement as much checker as you can on interface.
6. Assertion based verification environment is useful to catch bug in signal behavior.
7. Cover point will help to calculate functional coverage.
8. Code coverage will help on verification environment completion.
Keep your environment simple but robust, dont not allowed anyone to change a single bit/letter without head permission. Take coverage in account , look for code coverage figure which tell you how much code was hit by your testcases.
In my words, verification is some thing like generate stimulus for design and monitor the response. To built verification environment.. one has to be cleared about the IO's definition. If verification engineer knows what to drive and more important when to drive... she/he can create environment very well. I am putting some points which may help you to understand the verification environment.
1. IO's definition should be clear.
2. Make a block diagram, most of the design follow a protocol, if that is the case then think about to have BFM to cover that part of functionality.
3. Monitor can be placed anywhere in environment, but mostly monitor will sit at the interface of design and verification environment. Monitor could be a active entity or could be a passive entity..depends on the functionality.
4. Verification engineer should always be thinking of how to break the logic...?? Today's designer are very smart ,they also do the sanity verification before handing over the design to verification engineer. So verification team will have to create corner cases .
5. One way to break design is .....implement as much checker as you can on interface.
6. Assertion based verification environment is useful to catch bug in signal behavior.
7. Cover point will help to calculate functional coverage.
8. Code coverage will help on verification environment completion.
Keep your environment simple but robust, dont not allowed anyone to change a single bit/letter without head permission. Take coverage in account , look for code coverage figure which tell you how much code was hit by your testcases.
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