What is the difference between clock skew and clock jitter?

 

Clock Skew

From the same clock source, say the clock goes to 2 different nodes/points (or say 2 different flip flops). Clock skew is the difference in arrival times of the same clock source at 2 different points.

To calculate the Clock skew - 

Clock Skew = Clock Arrival time at Capture Flop - Clock Arrival time at Launch Flop.

Here's how it affects Setup and Hold Checks.

Setup Check → Clock_to_Q delay of Launch Flop + Datapath or Combinational logic Delay + Setup-Time of Capture Flop < (Clock Period + Clock Skew)

Hold Check → Clock_to_Q delay of Launch Flop + Datapath or Combinational logic Delay > (Hold-Time of the Capture Flop + Clock Skew).

If you had +200ps clock Skew, then the setup-check gets relaxed by 200ps, but hold-check becomes harder to meet. (And vice-versa if you have -200ps clock skew).

Clock Jitter :

Sometimes some external sources like noise, voltage variations may cause to disrupt the natural periodicity or frequency of the clock. This deviation from the natural location of the clock is termed to be clock jitter.

Clock jitter is basically the deviation from the clock's ideal behavior. The clock edges aren't where you expected them to. Maybe +/- 50 ps off from your expectations. So this needs to be accounted for when analyzing setup/hold timing.

Clock jitter is modelled in Static Timing Analysis using set_clock_uncertainty commands. If you ever saw a STA timing report, you will notice Clock Uncertainty, OCV modelling etc. contributing to the Clock Skew.

To get a better understanding, I highly recommend looking up a timing report with clock path information populated, and studying the clock path. Study how the CRPR(clock recovery pessimism removal), clock uncertainty, derates etc. contribute in determining the Clock skew between launch and capture flops.

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