Correct way of Digital design RTL Coding

What is the efficient way to code the RTL ? 

Many of digital designers thinks the code he has written will be optimized by synthesis tools (design compiler or RTL compiler)  and think tool will understand the logic and will optimized the code and will give efficient hardware. 

This may be true sometimes but there is uncertainty about how tool will optimized the RTL code. 

Tool will understand the logic and optimized it but there could be chances when synthesis tool may screw up the design. Some guidelines are given below to avoid such scenarios. 

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Below are the steps to design micro-architecture of efficient hardware.

1. Collect all the requirements , IO's specification and timing diagram. ( All inputs)

2. Go for top to down approach, first come up with top level block diagram.

3. After initial block diagram, prepare data-flow for the design block.

4.At this moment , Specification of design must be clear , if there are any doubts , consult with related person and get it rectified. Any assumptions must clearly mentioned. 

5. Once data-flow and top level block diagram is prepared , then focus on each block and try to capture functionality which is common to all blocks,  design hardware for common functionality and share it with the blocks.

6. There must be center control for all block , design a FSM which control all the blocks.

7. If latency is not an issue for design then flop all the inputs/outputs of all the blocks. This will help in timing closure.

8. If working in multi-clock domain, then keep logic in separate files and synchronized them with sync blocks. sync blocks may be library specific and many companies are having there own special cells for synchronizers. all sync signals should use same sync module.

9. writing hardware is not a difficult task , anyone can write behavioral logic but coding style must be a mix of coding types.

10. Before writing hardware, your mind should be clear on logic and try to write most of logic in form of Gates.

11. You can break the design and write mix of structural and behavioral code so that you let synthesis tool to know what could be the possible hardware. 

12. Review all the attributes , how you want to  optimize the design , and what part of design would be dont_touch , dont_size.  

Remember , writing RTL is not a big task , documentation is the big task , if you able to document the design very well, you are done with the 70% of design  (my best guess)

Comments are most welcome , if there is any query regarding design issue , please post here , I will try my best to resolve them.