Clock Gating Circuits

why do we will need clock gating in digital design and what are the ways to implement ? 

Clock gating today is an important aspect of design, in general clock gating is used to save power in circuit.  Today's if you talking about any smart device,  the first thing people search is the battery power. A device will not be a good device if it can't go long atleast for a day.

Most of the power in a soc / design is eaten by the analog circuit,  for digital components,  dynamic power only consume when there is transition between levels,  0 to 1 ....or 1 to 0 ..

If a designer able to stop unwanted transition in digital domain  then this will result in saving some power,  but if in the functional mode,  some of the analog circuit can be turn off then this will result in saving a significant amount of power,  in most of the devices,  there are initial calibration / adaptation routine,  some of them required one time only after releasing power on reset releasing,those circuit can be turned off.

Power consumption calculation include dynamic and static power , Static power is depend on the library. During micro-architecture , if power optimization is one of the key then one can design a better architecture to save maximum amount of power during transition. 

One large portion of dynamic power is consumed by clock tree, since clocks will be running all the time if not taken care. Clock gating is one of the method to reduce clock transition. 

Below is one way of implementing clock gating.

One of the popular design is,  put a AND gate and gated the clock by enable / gate signal. If using enable signal then the chances are high you will get a glitch which deasserting enable signal even if it come through a sync flop,  one way to overcome this problem is, use negedge sync flop for enable signal,  this way enable signal will get half clock cycle to get settledown. 

Q. What is clock gating timing checks ? How Setup and Hold timing take care in clock gating ? 
  

To know more in detail about the Low Power Design, follow the link below

Low Power Design 
Clock gating analysis during synthesis