Table of Contents

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CONTENTS

1.Introduction : 

1.1  Career Growth in VLSI Industry

1.2  The Future of Semiconductor 

2. VLSI Topics

2.1  Semiconductor Job Portal - Intern & freshers  

2.2  Digital Design for Beginners and Professionals

2.3  Career Growth in VLSI Industry

2.4  The Future of Semiconductor 

2.5  Reason for limited entry scope for Freshers in VLSI

2.6  VLSI Industry Update

2,7  List of Semiconductor Companies

2.8  Top 10 VLSI companies

2.9  VLSI Industry Updates

2.10 Engineering Basics

2.11 Open Sourced FREE CAD/EDA VLSI tools 

2.12 List of top 10 companies in Semiconductor - 2021 

2.13 The best top 20 universities for MS in Digital VLSI in USA

2.14 Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar 

2.15 Question Answer on VLSI Semiconductor 

 3. Digital Design:

3.1  Low Power Design Technique

3.2  Reset Removal and Recovery Time 

3.3  AND , OR gate using 2:1 Mux

3.4  Draw a  2 input NAND gate using 2:1 mux

3.5  Low Power design and verification

3.6  Which gate power consumption better than reversible logic gate?

3.7  UPF Example 

3.8  SDC File -  A Sample file for Synthesis

3.9  Pos n Neg edge detector

3.10 Lockup Latches

3.11 Selective Signal dumping in VPD VCS

3.12 Async Reset or Sync Reset for ASIC ?

3.13 Digital PLL

3.14 Complex Number

3.15 DLL and PLL

3.16 How to make XOR gate using NAND

3.17 What is MTBF ?

3.18 One's Complement

3.19 Two's Complement

3.20 Error Correction and Detection - SECDEC

3.21 Running Disparity

3.22 Open Sourced FREE CAD/EDA VLSI tools 

3.23 Type of Adders with Verilog Code

3.24 VHDL operator 

3.25 Asynchronous FIFO with Programmable Depth

3.26 Asic Implementation Design Cycle 

3.27  Comparing AMBA AHB to AXI Bus using System Modeling. 

3.28 Difference between I2C or CAN protocol ? 

3.29  Retention Cells - UPF

4. Semiconductor Interface/Bus Protocols

4.1  List of Protocols (PCIe, USB , etc.)

4.2  I²C (Inter-Integrated Circuit)

4.3  Universal asynchronous receiver/transmitter

4.4  SPI

4.5  PCI-Express - Overview

4.6  Transaction Layer in PCI Express

4.7  Microwire IP Interface 

5. Verilog Tutorial /Crash Course

5.1  Verilog Introduction

5.2  Refreshing your brain with Verilog

5.3  Verilog - Data Types 

5.4  Verilog - Statements  

5.5  Verilog Design Style

5.6  Verilog - System Task

5.7  Verilog Operators

5.8  Verilog - Reserved KeyWords

5.9  Parameterized Modules in Verilog

5.10 Timescale in Verilog

5.11 File Handling in Verilog 

5.12 Blocking and Non-Blocking in Verilog 

6. RTL Design Code 

6.1  Verilog Projects

6.2  RTL Verilog Code for Design

6.3  PCIe_Project_Update

6.4  Verilog Code for the counting number of 1's and 0's 

6.5  Verilog code for Asynchronous and Synchronous Reset Flip-Flop

6.6  Verilog code to detect Pattern

6.7  Verilog Code for Gray to Binary Code Converter

6.8  Verilog code for module 

6.9  Verilog code for FIR FILTER

6.10 Verilog code for parity checker (even parity/odd parity)

6.11 Verilog code square root of a number

6.12 Verilog Code for Round Robin Algorithm

6.13 Verilog Code for Binary to 7-segment LED converter 

6.14 Verilog Code for modules

6.15 Verilog Code for 8-bit ALU

6.16 Verilog Binary to gray code conversion

6.17 Verilog code and FSM design to generating custom waveform 

6.18 Verilog code for Synchronous FIFO ( First In First Out  )

7. Clock Domain Crossing (CDC)

7.1  Clock Domain Crossing (CDC)

7.2  Convergence , divergence and re-convergence

7.3  CDC - Real time implementation

8. RTL Lint 

8.1  SpyGlass Custom Goal setup

8.2  Synchronizers list dump using SpyGlass Tool

9. STA

9.1  Unateness-> Positive Unate and Negative Unate

9.2  VLSI_EXPERT: Transition Violation in Semiconductor

10. Synthesis

10.1  .lib to/from .db conversion

10.2 fanout report on hierarchy in design in synthesis 

10.3 Physical Aware Synthesis 

11. Integrated-Circuit Fabrication

11.1 IC Fabrication : Interview Questions / Answers 

12. AHB-AXI Protocol 

12.1 How do split response and retry work for the AHB protocol?

12.2 Comparing AMBA AHB to AXI Bus using System Modeling.

13. PCIe Protocol 

13.1  PCI-Express - Overview

13.2  Transaction Layer in PCI Express

13.3  8b10encoder/decoder

13.4  Running Disparity

14. Solution  :Samir Palnitkar : A Guide to Digital Design and Synthesis 

14.1 Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar 

15. Place holder5

16. DAA

16.1  Left Edge Channel Algorithm for detailed routing

16.2  Dynamic vs Static Timing Analysis

16.3  DAA: Design and Analysis of Algorithm 

16.4  DAA: Design and Analysis of Algorithm - QA 

17. Scripting/Others

17.1  GNOME - Terminal while login in VNC

17.2  Shell Script Tutorial

17.3  GVIM Help

17.4  List of Perl Scripts used in post data processing

18. Interview Preparation

18.1  VLSI Interview Questions

18.2  Generic interview Questions

18.3  Interview question on AXI protocol

18.4  Implementation of Logical Questions 

18.5 Digital Design Interview Question on PCIe express 

18.6  Digital Design Interview Question on Synthesis

 

19. Academic/ Educational Projects with Micro-Architecture and Verilog code

19.1  RoadMap For Academic Projects 

19.2  PCI-Express - Overview

19.3  Transaction Layer in PCI Express

19.4  Microwire IP  

20. Verification

20.1  Key Points in Mixed Signal Design Verification

21. Physical Design

21.1  What is the difference between a DRC and a DRV in VLSI PD?

21.2 Physical Design - Common Questions  

22. General Question:

22.1  Logical Question

22.2  APTITUDE Question for Interviews

22B . VLSI Quiz 

22B.1  Quiz1 : Digital Design

23. Non-VLSI Topics:

23.1  Worst Hiring Stories

23.2  You need to remove these 6 items from your resume asap

23.3  Resume Guideline if you are applying for job as a Freshers.

23.4  10 Things to remember while considering the offers from your next employer

23.5  Are you looking for job change ?

23.6  How to negotiate for the best when making a move from your present employer ?

23.7  where an engineer/fresher can get the job ?

23.8 How to start a academic project 

23.9  Team Leadership Score check 

23.10 Team Leadership Question/Answer

23.11 Being productive while working from home 

24. Salary Around the Globe

24.1 Norway Salary - Average salary for Senior Software Engineer in Norway with 10+ years experience? 

24.2  Sweden Salary - An Average salary in Sweden for IT professional  

25. Job Opportunities in Norway 

25.1  Norway Salary - Average salary for Senior Software Engineer in Norway with 10+ years experience? 

25.2  Is it hard to get a job in Norway, as a foreigner?

25.3  Living cost in Norway , compared with India

 

26. Finland Opportunities in IT Sector

26.1  Moving to Finland from India , is it worth ?

27. Funny Posts ( non technical )

27.1 40+ Photos That Evoke a Lot of Curious Questions and Can’t Be Explained

Clock Gating Circuits

why do we will need clock gating in digital design and what are the ways to implement ? 

Clock gating today is an important aspect of design, in general clock gating is used to save power in circuit.  Today's if you talking about any smart device,  the first thing people search is the battery power. A device will not be a good device if it can't go long atleast for a day.

Most of the power in a soc / design is eaten by the analog circuit,  for digital components,  dynamic power only consume when there is transition between levels,  0 to 1 ....or 1 to 0 ..

If a designer able to stop unwanted transition in digital domain  then this will result in saving some power,  but if in the functional mode,  some of the analog circuit can be turn off then this will result in saving a significant amount of power,  in most of the devices,  there are initial calibration / adaptation routine,  some of them required one time only after releasing power on reset releasing,those circuit can be turned off.

Power consumption calculation include dynamic and static power , Static power is depend on the library. During micro-architecture , if power optimization is one of the key then one can design a better architecture to save maximum amount of power during transition. 

One large portion of dynamic power is consumed by clock tree, since clocks will be running all the time if not taken care. Clock gating is one of the method to reduce clock transition. 

Below is one way of implementing clock gating.

One of the popular design is,  put a AND gate and gated the clock by enable / gate signal. If using enable signal then the chances are high you will get a glitch which deasserting enable signal even if it come through a sync flop,  one way to overcome this problem is, use negedge sync flop for enable signal,  this way enable signal will get half clock cycle to get settledown. 

Q. What is clock gating timing checks ? How Setup and Hold timing take care in clock gating ? 
  

To know more in detail about the Low Power Design, follow the link below

Low Power Design 
Clock gating analysis during synthesis