There seems to be a conceptual gap between what you are trying to do, and the methods you are trying to do it with. Any type of RTL (register transfer logic) is going to be based on conventional logic, and just implementing the "logic" of a reversible gate will not have low power properties. Since it has more inputs and outputs, and therefore more transistors switching conventionally, then it will dissipate more power. That's what Cadence is telling you.
From what I can gather, trying to do this in CMOS VLSI is a research topic. There are not known techniques that are generally applicable, only experimental ones, and a complete dearth of any actual circuit examples on the web. There is a brief description of some of the techniques needed, such as a trapezoidal clock and gate transition rules at http://en.wikipedia.org/wiki/Adiabatic_circuit but not enough information to construct a circuit.
There have been quantum techniques demonstrated, but of course you won't be able to implement them in current VLSI processes, nor model them with Cadence.
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