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Nov 15, 2016

VLSI Interview Questions

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Hi All, This section of Question and answer will to refresh the memory , DO not use this as preparation of interview , long term it will not help. Please write your views in comments if you like this sections.

Please write answer in comments with respect to question if you know, I will update the questions with answer. It will help me and I can write answer to questions which is not answered.

Write your answer in comment with Q number
If you have any more questions and would like to add, please put it in comments.

My Blog includes -

Digital Design Interview Questions
I2C interview questions
Serial peripheral interface interview questions
Synthesis and timing related interview questions

Few more topics which may help you to find good job.

Q1. Design a FSM which can detect 1010111 pattern.

Q2. FIFO Design.

Q3. What is the difference in D-flop and T-flop ?
D flop is data flop, input will sample and appear at output after clock to q time. T flop is toggle flop, input will be inverted at output.

Q4. Define setup window and hold window ?
setup time -  time where data should be stable before active edge of clock.
hold time - time where data should be stable after active edge of clock.

Q5. What is the effect of clock skew on setup and hold ?
There is useful clock skew , in which if clock edge is delayed then it will buy sometime for setup but hold margin will reduce.  And if clock edge is coming before the expected edge then it will increase the hold time but reduce the setup window. 

 Q6. In a multicycle path, where do we analyze setup and where do we analyze hold ?
Thus, a multicycle path setup specified as N (cycles) should be accompanied by a multicycle hold constraint specified as N-1 (cycles).

Q7. How many test clock domains are there in a chip ?
There could be n number of clock domains , it's totally depends on DFT configuration. 

Q8. How enables of clock gating cells are taken care at the time of scan ?
All the enables signals are having test mux prior to clock gate, during test_mode, those enables are set to '1' and clock will pass through the clock gating cells.

Q9. Difference between functional coverage and code coverage ?
Code coverage cover the number of lines,  expression coverage , FSM coverage , etc while functional coverage will have a matrix where functionality of the design would be mapped to the test cases to measure the functional coverage.


Q10. Does 100% code coverage means 100% functional coverage & vice versa?

Q11. What do you mean by useful skew ?


Q12. What is shift miss and capture miss in transition delay faults ?

Q13. What is the structure of clock gating cell ?
A simple structure is AND gate , where one of the input is clock and other input is enable. 

Q13a. What is glitch free clock gating cells ? 

Q14. How can you say that placing clock gating cells at synthesis level will reduce the area of the design ?

Q15. How will you decide to insert the clock gating cell on logic where data enable is going for n number of flops ? 


Q16. What is the concept of synchronizers ?


Q17. What are lockup latches?


Q18. What is the concept of power islands ?

Q19. What does OCV, Derate and CRPR mean in STA ?

Q20. What is dynamic power estimation ?

Q21. On AHB bus which path would you consider for worst timing ?

Q22. What is the difference between blocking & non-blocking statements in verilog ?

Q23. What are the timing equations for setup and hold, with & without considering timing skew ?

Q24. Design a XOR gate with 2-input NAND gates

Q25. Design AND gate with 2X1 MUX

Q26. Design OR gate with 2X1 MUX

Q27. Design T-Flip Flop using D-Flip Flop

Q28. In a synchronizer how you can ensure that the second stage flop is getting stabilized input?

Q29. Design a pulse synchronizer

Q30. Calculate the depth of a buffer whose clock ratio is 4:1 (wr clock is fatser than read clock)

Q31. Design a circuit that detects the negedge of a signal. The output of this circuit should get deasserted along with the input signal

Q32. Design a DECODER using DEMUX

Q33. Design a FSM for 10110 pattern recognition

Q34. 80 writes in 100 clock cycles, 8 reads in 10 clock cycles. What is the minimum depth of FIFO?
Synchronous FIFO Interview Question

Q35. Why APB instead of AHB ?

Q36. case, casex, casez if synthesized what would be the hardware

Q37. Define monitor functions for AHB protocol checker

Q38. What is the use of AHB split, give any application

Q39. Can we synchronize data signals instead of control signals ?

Q40. What is the difference between a Verilog task and a Verilog function?



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Interview questions on blocking and non-blocking 
Q41. Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end


Q42. What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;

Q43. What is difference between freeze deposit and force?

Q44. What are the difference between Verilog and VHDL?

Q45. How can you model a SRAM at RTL Level?

Q46. What are different types of timing verifications?

Q47. What is the difference between Formal verification and Logic verification?

Q48. What is the difference between testing and verification?

Q49. What is the difference between Blocking and non-blocking statements ?

Blocking statement - evaluation and execution done before executing next statement

Non-Blocking statement - Evaluation done first for all statement in always block and then execution happens.

Q50. What is ASIC Design flow ?

Q51. What is slew – slew rate ?

Q52. What is skew – clock skew ?

Q53. What do you understand by a Loopback why is it needed ?

Q54. 80 MHz DDR – what do you understand from this ?

Q55. Why is PRBS needed in a tester ?

Q56. What do you understand by drive strength ?

Q57. What happens when you decrease the clock frequency – does setup / hold time violations at say 300MHz frequency vanish at 3 MHz ?

Q58. What is Latch and Flip-Flop ?

Q59. What is Decoder design, please explain address decoder,  how it works given x number of rows and columns draw timing and circuit ?

Q60. What is metastability ?

Meta-stability is state where flop output is unknown , it may be 0 or. Flop will be in metastable state when any timing requirement is violated and in that window any glitch or noise can change the state of flop.



Q61. What do you understand by synthesis ?

Q62. What are the RTL coding to make design a low power design ?

Q63. Write a Verilog code for synchronous and asynchronous reset?

Q64. What does `timescale 1 ns/ 1 ps' signify in a verilog code?

Q65. How to generate sine wav using verilog coding style?

Q66. How do you implement the bi-directional ports in Verilog HDL?

Q67. How to write FSM is verilog?

Q68. What is verilog case ?

Q69. What are inertial and transport delays ?

Q70. Will case always infer priority register? If yes how? Give an example.

Q71. What is file I/O?

Q72. What is general structure of Verilog code you follow?

Q73. In a pure sequential circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?

Q74. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?

Q75. What is sensitivity list?, If you miss sensitivity list what happens?

Q76.  How blocking and non blocking statements get executed?


Q77. How to avoid latches in your design?

Q78. What is difference between Verilog full case and parallel case?

Q79. What is the difference between casex, casez and case statements?

Q80. What is the difference between "= =" and "= = =" ?

Q81. What is a compiler directive like 'include' and 'ifdef'?

Q82. Write a verilog code to swap contents of two registers with and without a temporary register?

Q83. What is the difference between inter statement and intra statement delay?

Q84. What is delta simulation time?

Q85. What is the difference between task and function?

Q86. What is the difference between bit wise, unary and logical operators?



Q87. What is the difference between wire and reg?

Q88. What is the difference between $display and $monitor and $write and $strobe?

Q89. Design posedge detector circuit and write verilog code for it.

Q90. Design negedge detector circuit and write verilog code for it.

Q91. What is the concept of synchronizers ?
Synchronizers are to sync data from clock domain 1 to clock domain 2, , sync cell prevent metastability when signal from clock domain 1 is sampled in clock domain 2.

Q92. Does 100% code coverage means 100% functional coverage & vice versa?

Q93. Difference between functional coverage and code coverage ?

Q94. What is Slack ?
Slack is margin for the timing path, it could be negative or positive.

Q95. Design a pulse synchronizer.

Q96. Design a reset synchronizer.

Q97. How will you fix the setup and hold violation?

Q98. What are the constraints you used for the synthesis? Who decides the constraints?

Q99. What is uncertainty?

Q100. What is false path and multi cycle path?


Q101. What strategies used for the power optimization for your recent project?

Q102. Why max and min capacitance required?

Q103. What is jitter?

Q104. What is clock latency? How to specify? What is the command for that?

Q105. What is dynamic timing analysis? What is the difference with static timing analysis? Which is accurate? Why it is accurate?

Q106. Design a 4-bit subtractor circuit.

Q107. How to handle Asynchronous reset ?

Q108. What will happen if while synthesis we declare wrongly a path multi cycle path which was not multi cycle path ?


Q109. Steps to calculate FIFO dept.
A. To calculate , how much is the depth required,
  1. first take worst case at write side. 
  2. Once you know the time frame of worst case, calculate the data rate, calculate time and how many bits/bytes coming in to that time frame.
  3. Calculate how many read bits going out in that time frame.
  4. Once you know the in coming data and out going data in that worst case time frame , left over data should be required depth of FIFO.
Synchronous FIFO Interview Question
Q110. Which is important to close, setup violation or hold violation ? and why ?
Q111. One of chip is having hold violations after tape out, how to fix it ?

Q112. Design a circuit that calculates the square of a number.
           It should not use any multiplier circuits, use only mux and other logic.

Q113. What is the race condition ?

Q114. What is clock skew , how to minimize the clock skew ?

Q115. How to find the rotation direction of a circle , design minimum hardware to find the direction.

Q116.What is glitch , how to fix glitch in design ?

Q117. What is the diff between parameter and localparam ?

Verilog HDL local parameters are identical to parameters except that they cannot directly be modified by defparam statements or module instance parameter value assignments. Local parameters can be assigned constant expressions containing parameters, which can be modified with defparam statements or module instance parameter value assignments.

Q118. Detect number of one's or zero's in 8-bit  using combo logic ? 

Q119. Design a comparator which gives 1 when both the bits r same and zero when not same.. 

Q120.
I.There are 16 address line and 18 data line
II. and 12 address line and 16 data line ..what will be the memory size in both cases.

Q121. What is the importance of scan in digital system.

Q122.
4.Given A XOR B =C, such that prove the following
a. B XOR C =A
b. A XOR BXOR C=0;

Q123. Construct an input test pattern that can detect the result E stuck at 1 in the ckt below
NAND (A,B)->E, NAND(C,D)->F
AND(E,F)->A.

Q124. Make a JK FF using a D FF and 4->1 MUX.

Q125. Use 2->1 MUX to implement the following _expression
Y=A+BC’+BC(A+B).


Q126. Design a asyncronous circuit for the following clk waveforms. CLK->thrice the CLK period->half the period of input.

Q127. What is the setup time and hold time parameters of the FF, what happens if we are not consider it in designing the digital ckt.

Q128. Given two DFF A,B ones output is the input of other and have the common clock.
Fmax if A and B are +ve edge triggered, if A is+ve edge triggered ,B is -ve edge triggered what is the Fmax relation to previous Fmax relation…

Q129.
Two +ive triggered FFs are connected in series and if the maximum frequency that can operate this circuit is Fmax. Now assume other circuit that has +ive trigger FF followed by –ive trigger FF than what would be maximum frequency in terms of the Fmax that the circuit can work?

Q130. If you connect the input of an inverter to its output where will the output gets settled?
Ans. The output will settle at the logical threshold of the inverter ideally at VDD/2.

Q131.  The Vt of the transistor increases or decreases with the temperature.
Ans. The Vt of the the transistor decreases with temperature?

Q132. According to the saturation current equation the current through the transistor increases as Vt of the transistor decreases but it is not the case in practical situation, the reason is ?
Ans. The reason is the mobility of the charge carriers as it is the more prominent factor in the ON current equation and it decreases with the temperature.

Q133. What is channel length modulation and how it occurs?
Ans. Channel length modulation is the shortening of the channel length after Pinch off occurs, this causes the saturation current to increase linearly with Vds. This occurs due to the widening of the depletion region between drain to bulk region, primarily in the channel.

Q134. What are short channel effects, is channel length modulation also a short channel effect?
Ans. In short channel technologies, vertical electric field loses its complete control over the channel. That is gate loses its control over the channel as the horizontal electric field starts interfering with the channel formation. The most prominent effects are subthreshold leakage, velocity saturation. No, channel length modulation is not a short channel effect as it occurs after pinch off point, while short channel effects are mostly pre or during channel formation.

Q135. How does a Vt of transistor varies with temperature and doping and why?
Ans. The Vt of the transistor decreases as the temperature increases as minority carrier concentration increases, while Vt of the transistor decreases with increased doping as more majority carriers needs to be pushed into the bulk to create the depletion region before channel formation.

Q136. The value of the capacitance between gate to bulk for an NMOS transistor is maximum in which region of the MOS?
Ans. The gate to bulk capacitance is maximum for the cutoff region of the transistor.

Q137. Considering a 3 terminal NMOS device if a supply of Vdd is connected to the gate of a NOMS having Vt as the threshold value, and the supply voltage of Vdd is connected to either of the remaining terminal, In which of the region does the NMOS is in, and what is the output voltage at the remaining terminal?
Ans. The transistor being an NMOS works in saturation region, and being an NMOS its weak pull up, the output voltage will be Vdd-Vt.

Q138. Considering the question above if we connect another NMOS with its drain connected to the output of the previous NMOS and gate being connected to Vdd, then in which region does this NMOS operates in and what is the output voltage?
Ans. The transistor works in saturation region, the output voltage will be Vdd-Vt. The first transistor is connected to Vdd which make it’s Vds as Vdd -(Vdd-Vt) which is greater than Vgs-Vt, for the second transistor it can pass the voltage level up to which Vgs = Vt, this means it can also pass the full Vdd – Vt potential which is at its drain, also here Vds = Vgs– Vt, so it also works in saturation region.

Q139. If the voltage Vsb that is source to bulk voltage difference is increased in an NMOS how does Vt varies and why?
Ans. The Vt of the transistor increases, as the depletion region around the p-n junction increases and it takes more gate voltage to offset that charge.

Q140. How a latch gets inferred in RTL design?
Ans. A latch gets inferred in the RTL design:-
A)When there is no “else / default” statement in the “if / case” statements; in short if all possibilities of the conditions are not covered.
B)When all the outputs reg are not assigned the values in every condition of the “if / case” statement and some are left out, on the left out signals a latch gets inferred.

Q141. Does a latch get inferred when there is no else statement but multiple ifs covering whole functionality?
Ans. Conceptually no latch should be inferred but sometimes the synthesis tools are not intelligent enough and they might infer a latch. In order to avoid that, the safest way is to use an “else / default” statement in “if / case” respectively.

Q142. If there is an asynchronous feedback loop what is the problem?
Ans. If there is an asynchronous loop in the design the circuit becomes oscillatory or it may reach a stable state where it might get hung and it could not get out.

Q143. If an oscillatory circuit is there; what happens during (a) RTL Synthesis (b) Simulation?
Ans.
(a) During the RTL synthesis, the synthesis tool will give a warning during synthesis about the combinatorial feedback loop.
(b) During the simulation the simulation will get stopped saying the Iteration limit reached.

Q144. Where can we use Linting tools ? Can we use them to debug syntax?
Ans. Linting tools are used to evaluate the design for the synthesizability of the design. These tools are use to check for potential mismatches between simulation and synthesis. No they are not used to check the syntax.


Q145. What can be done to break the combinational loop?
Ans. By adding synchronous elements in the path. If it is really needed and if the design permits then by adding the buffers in the path.

Q146. why we use B.A (Blocking Assignments) and N.B.A (Non Blocking Assignments)?
Ans. B.A are used to model combinatorial logic as the value is of continuous assignment and doesn’t depend on the previous value, while N.B.A are used to model sequential circuits as the previous value is needed to propagate.

Q147. What will be the output of the following code?
always ( * )
begin
a <= b + d;
a <= c + b;
end
Ans. This is actually a race condition and the tool will take the last assignment on “a”.

Q148. Explain how Verilog is different to normal programming language?
A.Verilog can be different to normal programming language in following aspects
Simulation time concept
Multiple threads
Basic circuit concepts like primitive gates and network connection

Q149. Explain what is Slack?
A.Slack is referred as a time delay difference from the expected delay to the actual delay in a particular path. Slack can be negative or positive.

Q150.One path is having setup violations, since the path was false path, you set this path to false_path.
After declaring this path as false path, if you do report_timing on same path, what will be the output ?

CMOS related questions:
1. Explain working principle and construction of mosfet
2.How mosfet work like a switch and amplifier explain
3.All the second order effects in mosfet
4.Difference between short channel mosfet and long channel mosfet
5.Why do we go only for the scaling of width but not the length
6.CMOS delay related question
7.Stick diagram
8.VLSI design flow
9.VLSI technology flow
10.Question related to BiCMOS
11.If you interchange the pmos and nmos in CMOS inverter, will it still work like a inverter…if not then what will be its properties??
12.Why we prefer enhancement mosfet over depletion mosfet?
13.Explain CMOS latchup?
14.Why do we prefer NAND over NOR for digital designs?
15.How logical effort is always 2 for multiplexer??
16.CMOS inverter input output characteristics.




16 comments:

  1. Q3 ) A - D flop is data flop, input will sample and appear at output after clock to q time. T flop is toggle flop, input will be inverted at output.

    ReplyDelete
    Replies
    1. T flop is a toggle ff , input will be Inverted only when input is 1

      Delete
  2. Q94 ) Slack is margin for the timing path, it could be negative or positive.

    ReplyDelete
  3. Q91 ) Synchronizers are to sync data from clock domain 1 to clock domain 2, , sync cell prevent metastability when signal from clock domain 1 is sampled in clock domain 2.

    ReplyDelete
  4. Blocking statement - evaluation and execution done before executing next statement

    Non-Blocking statement - Evaluation done first for all statement in always block and then execution happens.

    ReplyDelete
  5. Nice.. It helps.

    ReplyDelete
  6. Q4 setup time - time where data should be stable before active edge of clock.
    hold time - time where data should be stable after active edge of clock.

    ReplyDelete
  7. Q60
    Meta-stability is state where flop output is unknown , it may be 0 or. Flop will be in metastable state when any timing requirement is violated and in that window any glitch or noise can change the state of flop.

    ReplyDelete
    Replies
    1. Metastability means state between 1 and 0.usually can see in bi stable circuitry.

      Delete
    2. Metastability means state between 1 and 0.usually can see in bi stable circuitry.

      Delete
  8. Ans 22. In a block, blocking statements are executed sequentially while non blocking statements are executed concurrently.

    ReplyDelete
  9. Q.5) Positive skew helps to address Set_up, as SKEW will be Subtracted from the DATA_PATH Tperiod>=Tc2q+Tcombo+Tsetup-Tskew(added in the clock_path; Tperiod+Tskew>=Tc2q+Tcombo+Tsetup); but for HOLD Thold+Tskew<=Tcombo+Tc2q.

    But Negative Skew will be problem for Set_up and good for hold.

    ReplyDelete
  10. in Simple, Positive Skew helps to SET_UP, creates problem for HOLD. Vice Versa in the Negative skew case.

    ReplyDelete
  11. Q.11) Intentionally added SKEW in the CLOCK path to get Benefit either for SET_UP, or to improve Clock period Delay called as useful SKEW

    ReplyDelete
  12. Q150) FALSE _PATHS are neglected from the STA Calculation. So We will have new Critical Path but not that FALSE_PATH.

    ReplyDelete
  13. Q.147. This is called as Write Write race condition. We cant make sure that which one is going come as output.

    ReplyDelete