Top 10 Digital Design Synthesis Interview Questions

Interview Prep

Top 10 Questions Asked in
Digital Design Synthesis Based Interviews

Q1

What are the various Design constraints used while performing Synthesis for a design?

📄 See the Answer →

Q2

What are the various design changes you do to meet design power targets?

📄 See the Answer →

Q3

What is meant by Library Characterizing?

📄 See the Answer →

Q4

What is meant by Wireload Model?

📄 See the Answer →

Q5

What are the measures to be taken to design for optimized area?

📄 See the Answer →

Q6

What are the key aspects while performing floorplan aware synthesis?

📄 See the Answer →

Q7

What are the measures in the Design taken for Meeting Signal-integrity targets?

📄 See the Answer →

Q8

What is the difference between Timing Constraints and Physical Constraints in Synthesis?

Timing constraints define the functional timing requirements of the design — clock definitions, clock periods, input/output delays, false paths, multicycle paths, and min/max delays. These are provided through SDC (Synopsys Design Constraints) files and guide the synthesis tool to meet the performance targets.

Physical constraints, on the other hand, define physical placement and routing rules such as blockages, pin placements, layer assignments, density constraints, and area targets. These are typically handled in the floorplanning and P&R stages rather than synthesis. In synthesis, the tool primarily optimizes for timing, area, and power using timing constraints, while physical constraints become more relevant in downstream physical design flows.

Q9

What are False Paths and Multi-cycle Paths, and when do you use them?

False Paths: A false path is a path in the design where data does not actually need to meet timing constraints because the signals are either independent or the path is logically never exercised. For example, when an asynchronous FIFO's read and write clocks are independent, the path crossing between them should be marked as a false path using set_false_path. This tells the synthesis tool not to optimize for timing on that path, freeing up resources for critical paths.

Multi-cycle Paths: A multi-cycle path is a path that has more than one clock cycle to propagate its data. For example, if a signal is registered on the rising edge of the clock and consumed two cycles later, it has a 2-cycle path. This is specified using set_multicycle_path with the -setup and -hold flags. This tells the tool to relax the timing requirement, allowing the use of slower cells or longer routing paths, which can save power and area.

Q10

What is the role of a Wireload Model and how does it differ from Parasitic Extraction?

A Wireload Model is a statistical estimation of wire delay and capacitance based on fanout, used during synthesis when actual physical routing information is not yet available. It provides a rough estimate of interconnect effects so the tool can make logical decisions about cell sizing and path optimization.

On the other hand, Parasitic Extraction is performed after physical design (placement and routing) when actual wire geometries, lengths, and layer assignments are known. Parasitic extraction produces accurate RC (resistance and capacitance) values for every net, stored in SDF (Standard Delay Format) or OpenAccess format.

The key difference is that wireload models are estimates used during synthesis, while parasitic extraction provides accurate measurements used for final timing sign-off in STA.

📚 Table of Contents →  

Verilog code for 8b/10b encoder and decoder

8b/10b is used mainly for clock recovery in serial communication. With this coding, the serial line will always get a balanced stream of 0's and 1's which give enough switching of 0's and 1's level on the line. It is called DC balancing.
Using this encoding will result in 25% overhead in the data stream , meaning to transmit 80-bits , you will actually transmit 100-bits.

To understand the encoding/decoding , it is highly recommended to read about the "running disparity".


Note that in the following tables, for each input byte, A is the least significant bit, and H the most significant. The output gains two extra bits, i and j. The bits are sent low to high: a, b, c, d, e, i, f, g, h, and j; i.e., the 5b/6b code followed by the 3b/4b code. This ensures the uniqueness of the special bit sequence in the comma codes.

The residual effect on the stream to the number of zero and one bits transmitted is maintained as the running disparity (RD) and the effect of slew is balanced by the choice of encoding for following symbols.

The 5b/6b code is a paired disparity code, and so is the 3b/4b code. Each 6- or 4-bit code word has either equal numbers of zeros and ones (a disparity of zero), or comes in a pair of forms, one with two more zeros than ones (four zeros and two ones, or three zeros and one one, respectively) and one with two less. When a 6- or 4-bit code is used that has a non-zero disparity (count of ones minus count of zeros; i.e., −2 or +2), the choice of positive or negative disparity encodings must be the one that toggles the running disparity. In other words, the non zero disparity codes alternate.
Below is the code for encoder and decoder. Contact me for the soft copy of RTL code.

Encoder Implementation Details ->

Implementation will be based on LUT which can be found in PCIe Specification.

Encoder Pin Descriptions

Name	Type	Descriptions
Clk	I	Encoder Clock. This pin is the main clock of the encoder. All registered inputs and outputs of the encoder are based on the rising of this clock.
Rstn	I	Active Low reset
Data_in[7:0]	I	8-bit data input
kchar	I	Control input
disp_in	I	Running Disparity Input. This pin provides to the encoder the running disparity before the encoding of current 8-bit data on datain_8b bus. 0 - -ve disparity 1 - +ve disparity
data_out[9:0]	O	Encoded data out
disp_out	O	Running disparity output
err	O	Invalid control character requested

Verilog code for 8b/10b encoder
-------------- Verilog Code Start ----------------
WIP

-------------- Verilog Code End  ----------------

Verilog code for 8b/10b decoder
-------------- Verilog Code Start ----------------
WIP 

-------------- Verilog Code End  ----------------

Testbench for the Verilog code , Instantiated encoder and decoder. 

Thanks for visiting the Blog , please share your comments.

Ref - https://en.wikipedia.org/wiki/8b/10b_encoding

Digital Design Interview Question on PCIe express

Digital Design Interview Question on PCIe express :




What are the PCIe protocol extensions, and how do they improve PCIe interconnect performance?
The PCIe protocol extensions are primarily intended to improve interconnect latency, power and platform efficiency. These protocol extensions pave the way for better access to platform resources by various compute- and I/O-intensive applications as they interact with and through the PCIe interconnect hierarchy. There are multiple protocol extensions and enhancements being developed and they range in scope from data reuse hints, atomic operations, dynamic power adjustment mechanisms, loose transaction ordering, I/O page faults, BAR resizing and so on. Together, these protocol extensions will increase PCIe deployment leadership in emerging and future platform I/O usage models by enabling significant platform efficiencies and performance advantages.




Section 4.2.4.2 - When upconfiguring a Link in the LTSSM Configuration.Linkwidth.Start state, are the Lanes which are being activated required to transmit an EIEOS first when they exit Electrical Idle?

No. Lanes being activated for upconfiguration are not required to align their exit of Electrical Idle with the transmission of any Symbol, Block, or Ordered Set type. Furthermore, the Lanes are not required to exit Electrical Idle before the LTSSM enters the Configuration.Linkwidth.Start state.



What is PCI Express (PCIe) 3.0? What are the requirements for this evolution of the PCIe architecture?

PCIe 3.0 is the next evolution of the ubiquitous and general-purpose PCI Express I/O standard. At 8GT/s bit rate, the interconnect performance bandwidth is doubled over PCIe 2.0, while preserving compatibility with software and mechanical interfaces. The key requirement for evolving the PCIe architecture is to continue to provide performance scaling consistent with bandwidth demand from leading applications with low cost, low power and minimal perturbations at the platform level. One of the main factors in the wide adoption of the PCIe architecture is its sensitivity to high-volume manufacturing materials and tolerances such as FR4 boards, low-cost clock sources, connectors and so on. In providing full compatibility, the same topologies and channel reach as in PCIe 2.0 are supported for both client and server configurations. Another important requirement is the manufacturability of products using the most widely available silicon process technology. For the PCIe 3.0 architecture, PCI-SIG believes a 65nm process or better will be required to optimize on silicon area and power.




Section 4.2.7.3 - PCIe 3.0 Base spec section 4.2.7.4 states that "Receivers shall be tolerant to receive and process SKP Ordered Sets at an average interval between 1180 to 1538 Symbol Times when using 8b/10b encoding and 370 to 375 blocks when using 128b/130b encoding.ÌÒ For 128/130 encoding, if the Transmitter sends one SKP OS after 372 blocks and a second after 376 blocks, the average interval comes out to be 374 blocks and that falls in the valid range. So is this allowed, or must every SKP interval count fall inside the 370 to 375 blocks?

At 8 GT/s, a SKP Ordered Set must be scheduled for transmission at an interval between 370 to 375 blocks. However, the Transmitter must not transmit the scheduled SKP Ordered Set until it completes transmission of any TLP or DLLP it is sending, and sends an EDS packet. Therefore, the interval between SKP OS transmissions may not always fall within a 370 to 375 block interval.

For example, if a SKP Ordered Set remains scheduled for 6 block times before framing rules allow it to be transmitted, the interval since the transmission of the previous SKP OS may be 6 blocks longer than normal, and the interval until the transmission of the next SKP OS may be 6 Blocks shorter than normal. But the Transmitter must schedule a new SKP Ordered Set every 370 to 375 blocks, so the long-term average SKP OS transmission rate will match the scheduling rate.

Receivers must size their elastic buffers to tolerate the worst-case transmission interval between any two SKP Ordered Sets (which will depend on the Max Payload Size and the Link width), but can rely on receiving SKP Ordered Sets at a long term average rate of one SKP Ordered Set for every 370 to 375 blocks. The SKP Ordered Set interval is not checked by the Receiver.




Section 4.2.6.4.2 - According to pg227 of spec, "When using 128b/130b encoding, TS1 or TS2 Ordered Sets are considered consecutive only if Symbols 6-9 match Symbols 6-9 of the previous TS1 or TS2 Ordered Set". When in Recovery.Equalization and if using 128b/130b encoding, is it required that lane/link numbers (symbol 2) match in TS1s to be considered as consecutive or is it need not match?

The Receiver is not required to check the Link and Lane numbers while in Recovery.Equalization.




Section 7.28.3 - When the maximum M-PCIe Link speed supported is 2.5 GT/s, what will be the Link speed following a reset?

The Link Speed following reset will be the result of Configuration process. During the M-PCIe discovery and Configuration process, RRAP is used to discover M-PHY capabilities, analyze and configure configuration attributes accordingly. Depending on the High speed supported by both components, the Link Speed and Rate Series may get configured for HS-G1, HS-G2 or HS-G3 and RATE A or B respectively. For this particular example Link Speed could be either HS-G1 or HS-G2 depending on the supported Link Speeds of the other Component on the LINK.




Section 4.2.6.9 - When in the Disabled state the Upstream Port transitions to Detect when an Electrical Idle exit is detected at the receiver. Is an Electrical Idle exit required to be detected on all Lanes?

An Electrical Idle exit is required to be detected on at least one Lane.




Has there been a new compliance specification developed for PCIe 3.0?

For each revision of its specification, PCI-SIG develops compliance tests and related collateral consistent with the requirements of the new architecture. All of these compliance requirements are incremental in nature and build on the prior generation of the architecture. PCI-SIG anticipates releasing compliance specifications as they mature along with corresponding tests and measurement criteria. Each revision of the PCIe technology maintains its own criteria for product interoperability and admission into the PCI-SIG Integrators List.




Section 4.2.6.6.1.3 - How can I configure the RC, if permissible, to send 4096 FTS to EP while RC transits out of L0s?

Setting the Extended Synch bit in the Link Control register of the two devices on the link will increase the number of FTS Ordered Sets to 4096, but the Extended Synch bit is used only for testing purposes

there is Interview audio recording on PCIe. this is purely google search. 

https://www.youtube.com/watch?v=DJ7ksMXAwsk 

Table of Contents

Implementation of Logical Questions

Coming soon with OOB questions and answer . stay tuned.

Please leave your comments if you want to add logical question or have any doubt.

Q1. Design a Lift controller. Below are the specification.

1. Life can move from flr-0 to flr-20.
2. There is only 1 lift.
3. Priority should be given if input given from inside of lift.

Prepare the document first, after that RTL coding in verilog.


Q2. Continue with Q1, there is one more life.  All specifications are same.
Design the controller efficiently.

Prepare the document first with analysis part. how many conditions will be there and what will be the decision.  Round robin/ Priority based arbitration can be used to resolve conflict.

Q3. Traffic light controller using verilog.
Specification -
Consider a controller for traffic light at the intersection of four roads. Consider R1, R2, R3 and R4 as four roads and PL as Pedestrian. The road has the following stages.
Green=10011, Yellow=01000,  Red=00100.

The pedestrian has following two states
Green=0000  ,Red=1111

First the road R1 is green and all other roads R2, R3 ,R4 and PL are red .After a some delay R1 is turn to yellow and then red the traffic signal on R2 is green. After a delay R2 is turn to yellow and then red the signal on R3 is green.Then R3 is changed to yellow and then red. Similarly R4 is turned green then yellow & then red. Pedestrian Light PL is green after a delay. Again R1 is turned to green & the routine will continue.

Q4.  Continuation from Q3 , with all specification in Q3,  each road having one sensor.  Sensor sense the traffic and it give output to traffic light mechanism if no vehicle cross it for a time period. Based on the input from sensor, traffic light can change the state.

Q5. Design a hardware to count the number of 1's and 0's in 40-bit data. Data is coming continuously.

Table of Contents

How to make XOR gate using NAND

Interview questions on Digital Design - How to make Xor gate using NAND .

Step by Step approach -> 

Lets say input is A and B

Xor  -  A.(!B) + (!A).B

NAND -  !(A.B)

Below is the calculation done for make XOR gate using NAND gate using 4 NAND gate.

Table of Contents