VLSI & SoC Design Practice Hub
Select a subject domain below to access specific technical test modules.
Verification
Test plans, functional coverage metrics, and simulation-based strategy tracks.
Digital Design Fundamentals
Combinational logic structures, state machines, and fundamentals of sequential circuits.
Static Timing Analysis
Setup/hold constraints, timing violations, false paths, and SDC constraints.
UVM Framework
Universal Verification Methodology components, TLM ports, phases, and factories.
Clock Domain Crossing (CDC)
Metastability issues, multi-clock synchronization techniques, and asynchronous FIFOs.
Logic Synthesis
Translation mechanics, logic optimization steps, and gate-level netlist generation.
