Coming soon with OOB questions and answer . stay tuned.
Please leave your comments if you want to add logical question or have any doubt.
Q1. Design a Lift controller. Below are the specification.
1. Life can move from flr-0 to flr-20.
2. There is only 1 lift.
3. Priority should be given if input given from inside of lift.
Prepare the document first, after that RTL coding in verilog.
Q2. Continue with Q1, there is one more life. All specifications are same.
Design the controller efficiently.
Prepare the document first with analysis part. how many conditions will be there and what will be the decision. Round robin/ Priority based arbitration can be used to resolve conflict.
Q3. Traffic light controller using verilog.
Specification -
Consider a controller for traffic light at the intersection of four roads. Consider R1, R2, R3 and R4 as four roads and PL as Pedestrian. The road has the following stages.
Green=10011, Yellow=01000, Red=00100.
The pedestrian has following two states
Green=0000 ,Red=1111
First the road R1 is green and all other roads R2, R3 ,R4 and PL are red .After a some delay R1 is turn to yellow and then red the traffic signal on R2 is green. After a delay R2 is turn to yellow and then red the signal on R3 is green.Then R3 is changed to yellow and then red. Similarly R4 is turned green then yellow & then red. Pedestrian Light PL is green after a delay. Again R1 is turned to green & the routine will continue.
Q4. Continuation from Q3 , with all specification in Q3, each road having one sensor. Sensor sense the traffic and it give output to traffic light mechanism if no vehicle cross it for a time period. Based on the input from sensor, traffic light can change the state.
Q5. Design a hardware to count the number of 1's and 0's in 40-bit data. Data is coming continuously.
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