Floorplan Aware Synthesis

Key floorplanning measures to improve wire-length, routability, area utilization, and power integrity.

Floorplan Guidelines

Floorplanning is not only “placing blocks”; it is about making early decisions that minimize routing risk, reduce timing closure iterations, and improve overall chip quality.

Placement based on dataflow & connectivity

• Study the data-flow graph of the design and place the blocks accordingly, to reduce the weighted sum of area and wire-length.
• Place blocks based on accessibility/connectivity, thereby reducing wire-length.
• If a memory communicates to the outside world more frequently, placing it at the boundary makes much more sense.

Shape, notches & abutment

• Minimize the usage of blocks other than square/compact shapes.
• Avoid blocks having notches (they often create congestion and unusable whitespace).
• Abut the memory if the pins are one-sided; this can reduce both area and routing overhead.

Routability estimation (pins vs metal resources)

• Study the number of pins to be routed.
• With the minimum metal width allowed, estimate potential routability issues early.
• Use this insight to adjust block spacing, channels, and macro placement.

Tip: Pin-dense macros near each other without enough routing tracks is a common root-cause of congestion.

Power/ground noise consideration

• Study the architecture and application behavior.
• Blocks that will be enabled together should be scattered (spatially distributed) to reduce simultaneous switching impact and power-ground noise.
• Avoid clustering multiple high-activity blocks unless the power grid is strengthened accordingly.

Good floorplanning reduces wirelength, improves routability, and strengthens power integrity—before P&R starts.

Connectivity • Routability • PI

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