Each cell in design will have timing arcs, there are different types of arcs present in design. For example, for sequential cell , timing arc will be from clock to Q , for Combi logic, timing arc will be from input to output.
Each timing arc has a timing sense , with this output of cells changes with different types of transition happens on input. Position unate and negative unate is related to transition on timing arcs.
A Positive Unate is , rising transition on input causes output to rise and falling transition on input causes output to fall , a simple example is given below.
A Negative Unate is, rising transition on input causes output to fall , and falling transition on input causes output to rise , a simple example is given below.
A Non Unate is , output transition can not be determined from either on the inputs , for example a XOR gate where output of XOR depend on both inputs ..
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