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Quiz 1: Digital design Fundamentals Quiz2: Digital Design: CDC Link 1

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Mar 18, 2024

Quiz 2: Digital Design Fundamentals

1.

CDC : What do you use to avoid meta-stability due to clock domain crossing in design

T type flip flop

glitchless mux

synchronizers

reset the circuit

2.

CDC : What happens when design went into meta-stable state ?

Flop output set it to 0

Flop output set it between 0 and 1

flop output set it either 0 or 1

Flop output set it to 1

3.

CDC : Which tool we are using for CDC analysis ?

Spyglass

Genus

Fusion Compiler

Prime Time

4.

CDC : Can you detect CDC in static timing analysis

Yes

No

Can not say

Up to STA tool

5.

CDC : what factor determine the number of stage of flip-flop to be used in design ?

STA

MTBF

Design Frequency

transistor characteristics

6.

CDC : what do you use for asynchronous data transmission ?

req and ack

Asynchronous FIFO

Synchronous FIFO

Memory

7.

CDC : req and ack mechanism used when

signal is pulse type

signal is level type

signal is tie to 0

signal is tie to 1

8.

CDC: Which can catch a cdc violations ?

STA

IR drop analysis

GLS

None

This quiz has been created using the tool HTML Quiz Generator

Comments are welcome , you can put your score in comment :)

QUIZ -3 On Verilog

Posted by VLSI Expert - Rahul J

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2 comments:

kid_unltdMarch 19, 2024 at 9:27 AM
Check question 7 again.
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