RTL DIGITAL DESIGN

Practical ASIC , RTL , VLSI Knowledge

Mar 18, 2024

Quiz 2: Digital Design Fundamentals

Comments are welcome , you can put your score in comment :)

QUIZ -3 On Verilog

UPF Quizes - Universal power format

Posted by VLSI Expert - Rahul J

Email This BlogThis!Share to X Share to Facebook Share to Pinterest

2 comments:

kid_unltdMarch 19, 2024 at 9:27 AM
Check question 7 again.
ReplyDelete
Replies

Newer Post Older Post Home

Subscribe to: Post Comments (Atom)

Follow me on Insta

Follow Me

About Me

VLSI Expert - Rahul J

View my complete profile

Digital Design Blog

This blog is on Digital design , includes other related topics.

Blog_Insider

Home
Career Growth In Vlsi Industry
Semiconductor Job portal - Internship
VLSI world for Freshers
Future of Semiconductor
VLSI Projects
PLL or DLL
Complex Number
Serial Perepheral Interface
UART Design
I2C Design
How to make Digital PLL
Reset - Async or Sync ?
How to convert .db to .lib
How to verify Mixed signal design
Know about unateness
RTL technique for Low Power Design
Unified Power Format - UPF for Low Power
UPF Example
Refreshing Verilog for Interview
Low Power Design and Verification
Blocking and Non Blocking in Verilog
Gate Level Simulation
Code Coverage Analysis
BIST
Static Timing Analysis
SDC - Timing Constraint
Debugging Guideline for Functional Simulation
Clock Dividers and Multipliers
Correct way of Digital design RTL Coding
Digital Design for Beginner and Prof
Clock Gating Circuits
Handling multiclock domain in design ( RTL + SDC )
Implementation of Logical Questions
Step by Step approach to make XOR using NAND
APTITUDE QUESTIONS
Interview Questions on AXI
Edge detection logic with Verilog code
Gvim Help
Error Detection and Correction
Running Disparity
Verilog Code for the counting number of 1's and 0's
Verilog code for binary to gray code
Verilog Code for FIR Filter
Types of Adders with Verilog Code
VHDL Operator
Parameter in Verilog
SpyGlass Custom Goal
Dump Synchronizer using SpyGlass
Generic Interview Questions
Resume Guidelines - A must visit page
Analog IC Design
Left -Edge Algorithm
Max Transition Violation in Design
OCV, AOCV and POCV -Static Timing Analysis
you-need-to-remove-these-6-items
FREE CAD Tools
List of Semiconductor Comanies
The best top 20 universities for MS in Digital VLSI in USA

Top Visited Posts

VLSI Projects
100+ VLSI Digital interview questions
Roadmap For Educational Projects in VLSI

RTL Code

RTL for Asynchronous FIFO
RTL for cnt 0's n 1's
RTL for FIR Filter
RTL for Bin2Gray
RTL for 8-bit ALU
SPI Controller RTL code in Verilog
RTL for Pos/Neg Detector
RTL for Parity Checker
RTL Design for Gray to Binary
RTL for calculate square root
RTL for Round Robin Algo

Blog Posts

1. Pattern Detection 2. Gray to Binary code 3. FIR Filter 4. Round Robin Algorithm 5. LED converter 6. Binary to Gray 7. Synchronous FIFO

Search This Blog

Contact Form

Name

Email *

Message *

Followers

Search This Blog

Popular Posts

Table of Contents

Here is the blog site map. Feel free to post your feedback to improve it further. Insta Link to follow - MY Insta Prpfile - Follow...
RTL Digital Design Interview and Learning Hub

RTL Digital Design — VLSI Blog VLSI · RTL · Digital Design RTL Digital Design Interv...
Top 10 Digital Design Synthesis Interview Questions

Interview Prep Top 10 Questions Asked in Digital Design Synthesis Based Interviews Q1 What ar...
What are the various Design constraints used while performing Synthesis for a design ?

1. Timing C onstraints These comes under timing constraints , they are clock constraints like creating_clock, clock uncertainity . generati...
What are the various Design constraints used while performing Synthesis for a design ?

Design Power Optimization Strategies Various Design Changes to Meet Power Targets To achieve specific p...
Floorplan Aware Synthesis

Floorplan Guidelines Key floorplanning measures to improve wire-length , routability , ...
Convergence , divergence and re-convergence

Now a days , multiple clocks in a system are common due to increasing frequency and complexity. A CDC check is a must check on the design ...
Semiconductor Job Portal - Intern & freshers

This page is a collection of Internship/freshers jobs in semiconductor/embedded industry , source would be linkedin/online job portal. Upda...
Verilog Projects

Here are few Verilog Projects which can be used as educational projects. If you are looking for some tutorial to start a academic projec...
Gate Level Simulation

Below are the basic questions which should come in your mind if you are new to gate level simulation. What is gate level simulation and...

Search This Blog

Disable

All rights reserved, copyright to Rahul Jain. Simple theme. Theme images by TommyIX. Powered by Blogger.