About the Author
Welcome to my digital design blog! I share in-depth articles on RTL design, timing analysis, ASIC/FPGA concepts, and interview preparation.
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CONTENTS
1 Introduction
2 VLSI Topics
- 2.1Semiconductor Job Portal - Intern and Freshers
- 2.2Digital Design for Beginners and Professionals
- 2.3Career Growth in VLSI Industry
- 2.4The Future of Semiconductor
- 2.5Reason for Limited Entry Scope for Freshers in VLSI
- 2.6VLSI Industry Update
- 2.7List of Semiconductor Companies
- 2.8Top 10 VLSI Companies
- 2.9VLSI Industry Updates
- 2.10Engineering Basics
- 2.11Open-Sourced Free CAD/EDA VLSI Tools
- 2.12List of Top 10 Companies in Semiconductor - 2021
- 2.13Top 20 Universities for MS in Digital VLSI in the USA
- 2.14Solution: Verilog HDL - A Guide to Digital Design and Synthesis
- 2.15Questions and Answers on VLSI Semiconductor
- 2.16System-on-Chip Architecture
3 Digital Design
- 3.1Low Power Design Technique
- 3.2Reset Removal and Recovery Time
- 3.3AND and OR Gate Using 2:1 Mux
- 3.4Draw a 2-Input NAND Gate Using 2:1 Mux
- 3.5Low Power Design and Verification
- 3.6Gate Power Consumption and Reversible Logic Gates
- 3.7UPF Example
- 3.8SDC File - A Sample File for Synthesis
- 3.9Positive and Negative Edge Detector
- 3.10Lockup Latches
- 3.11Selective Signal Dumping in VPD VCS
- 3.12Async Reset or Sync Reset for ASIC?
- 3.13Digital PLL
- 3.14Complex Number
- 3.15DLL and PLL
- 3.16How to Make XOR Gate Using NAND
- 3.17What Is MTBF?
- 3.18One's Complement
- 3.19Two's Complement
- 3.20Error Correction and Detection - SEC-DED
- 3.21Running Disparity
- 3.22Open-Sourced Free CAD/EDA VLSI Tools
- 3.23Types of Adders with Verilog Code
- 3.24VHDL Operators
- 3.25Asynchronous FIFO with Programmable Depth
- 3.26ASIC Implementation Design Cycle
- 3.27Comparing AMBA AHB to AXI Bus Using System Modeling
- 3.28Difference Between I2C and CAN Protocol
- 3.29Retention Cells - UPF
4 Semiconductor Interface and Bus Protocols
- 4.1List of Protocols: PCIe, USB and Others
- 4.2I²C - Inter-Integrated Circuit
- 4.3Universal Asynchronous Receiver/Transmitter
- 4.4SPI
- 4.5PCI Express Overview
- 4.6Transaction Layer in PCI Express
- 4.7Microwire IP Interface
5 Verilog Tutorial and Crash Course
- 5.1Verilog Introduction
- 5.2Refreshing Your Brain with Verilog
- 5.3Verilog Data Types
- 5.4Verilog Statements
- 5.5Verilog Design Style
- 5.6Verilog System Tasks
- 5.7Verilog Operators
- 5.8Verilog Reserved Keywords
- 5.9Parameterized Modules in Verilog
- 5.10Timescale in Verilog
- 5.11File Handling in Verilog
- 5.12Blocking and Non-Blocking in Verilog
6 RTL Design Code
- 6.1Verilog Projects
- 6.2RTL Verilog Code for Design
- 6.3PCIe Project Update
- 6.4Verilog Code for Counting 1s and 0s
- 6.5Asynchronous and Synchronous Reset Flip-Flop
- 6.6Verilog Code to Detect Pattern
- 6.7Gray to Binary Code Converter
- 6.8Verilog Code for Module
- 6.9Verilog Code for FIR Filter
- 6.10Verilog Parity Checker
- 6.11Verilog Code for Square Root
- 6.12Verilog Code for Round Robin Algorithm
- 6.13Binary to 7-Segment LED Converter
- 6.14Verilog Code for Modules
- 6.15Verilog Code for 8-bit ALU
- 6.16Verilog Binary to Gray Code Conversion
- 6.17FSM Design for Generating Custom Waveform
- 6.18Synchronous FIFO RTL Code
- 6.19SPI Controller
- 6.20CRC Generator
7 Clock Domain Crossing
- 7.1Clock Domain Crossing
- 7.2Convergence, Divergence and Re-convergence
- 7.3CDC Real-Time Implementation
8 RTL Lint
9 Static Timing Analysis
10 Synthesis
- 10.1LIB to DB Conversion
- 10.2Fanout Report on Hierarchy in Design
- 10.3Physical-Aware Synthesis
- 10.4SDC File for DDR Memory
11 Integrated-Circuit Fabrication
12 AHB-AXI Protocol
13 PCIe Protocol
- 13.1PCI Express Overview
- 13.2Transaction Layer in PCI Express
- 13.38b10b Encoder and Decoder
- 13.4Running Disparity
14 Verilog HDL Solution Guide
15 Reserved Section
- 15.1More content will be added here.
16 Design and Analysis of Algorithms
- 16.1Left Edge Channel Algorithm for Detailed Routing
- 16.2Dynamic vs Static Timing Analysis
- 16.3Design and Analysis of Algorithm
- 16.4Design and Analysis of Algorithm - Questions and Answers
17 Scripting and Other Topics
- 17.1GNOME Terminal While Login in VNC
- 17.2Shell Script Tutorial
- 17.3GVIM Help
- 17.4Perl Scripts Used in Post Data Processing
18 Interview Preparation
- 18.1VLSI Interview Questions
- 18.2Generic Interview Questions
- 18.3Interview Questions on AXI Protocol
- 18.4Implementation of Logical Questions
- 18.5Digital Design Interview Questions on PCI Express
- 18.6Digital Design Interview Questions on Synthesis
19 Academic and Educational Projects
- 19.1Roadmap for Academic Projects
- 19.2PCI Express Overview
- 19.3Transaction Layer in PCI Express
- 19.4Microwire IP
20 Verification
21 Physical Design
- 21.1Difference Between DRC and DRV in VLSI Physical Design
- 21.2Physical Design Common Questions
- 21.3Filler Cells
- 21.4Clock Buffers and Clock Inverter
22 General Questions
22B VLSI Quiz
- 22B.1Quiz 1: Digital Design
- 22B.2Quiz 2: Digital Design
- 22B.3Quiz 3: Digital Design
- 22B.4Quiz 4: Digital Design
- 22B.5Quiz 1: UPF
- 22B.6Quiz 2: UPF
- 22B.7Quiz 3: UPF
- 22B.8Quiz 4: UPF
- 22B.9Quiz: UPF Level Shifter
- 22B.10Quiz: UPF Power Switch
23 Non-VLSI Topics
- 23.1Worst Hiring Stories
- 23.2Six Items to Remove from Your Resume
- 23.3Resume Guidelines for Freshers
- 23.4Things to Remember While Considering Offers
- 23.5Are You Looking for a Job Change?
- 23.6How to Negotiate When Changing Jobs
- 23.7Where Can an Engineer or Fresher Get a Job?
- 23.8How to Start an Academic Project
- 23.9Team Leadership Score Check
- 23.10Team Leadership Questions and Answers
- 23.11Being Productive While Working from Home
24 Salary Around the Globe
25 Job Opportunities in Norway
- 25.1Norway Salary for Senior Software Engineers
- 25.2Is It Hard to Get a Job in Norway as a Foreigner?
- 25.3Living Cost in Norway Compared with India
