Table of Contents

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CONTENTS

1.Introduction : 

1.1  Career Growth in VLSI Industry

1.2  The Future of Semiconductor 

2. VLSI Topics

2.1  Semiconductor Job Portal - Intern & freshers  

2.2  Digital Design for Beginners and Professionals

2.3  Career Growth in VLSI Industry

2.4  The Future of Semiconductor 

2.5  Reason for limited entry scope for Freshers in VLSI

2.6  VLSI Industry Update

2,7  List of Semiconductor Companies

2.8  Top 10 VLSI companies

2.9  VLSI Industry Updates

2.10 Engineering Basics

2.11 Open Sourced FREE CAD/EDA VLSI tools 

2.12 List of top 10 companies in Semiconductor - 2021 

2.13 The best top 20 universities for MS in Digital VLSI in USA

2.14 Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar 

2.15 Question Answer on VLSI Semiconductor 

 3. Digital Design:

3.1  Low Power Design Technique

3.2  Reset Removal and Recovery Time 

3.3  AND , OR gate using 2:1 Mux

3.4  Draw a  2 input NAND gate using 2:1 mux

3.5  Low Power design and verification

3.6  Which gate power consumption better than reversible logic gate?

3.7  UPF Example 

3.8  SDC File -  A Sample file for Synthesis

3.9  Pos n Neg edge detector

3.10 Lockup Latches

3.11 Selective Signal dumping in VPD VCS

3.12 Async Reset or Sync Reset for ASIC ?

3.13 Digital PLL

3.14 Complex Number

3.15 DLL and PLL

3.16 How to make XOR gate using NAND

3.17 What is MTBF ?

3.18 One's Complement

3.19 Two's Complement

3.20 Error Correction and Detection - SECDEC

3.21 Running Disparity

3.22 Open Sourced FREE CAD/EDA VLSI tools 

3.23 Type of Adders with Verilog Code

3.24 VHDL operator 

3.25 Asynchronous FIFO with Programmable Depth

3.26 Asic Implementation Design Cycle 

3.27  Comparing AMBA AHB to AXI Bus using System Modeling. 

3.28 Difference between I2C or CAN protocol ? 

3.29  Retention Cells - UPF

4. Semiconductor Interface/Bus Protocols

4.1  List of Protocols (PCIe, USB , etc.)

4.2  I²C (Inter-Integrated Circuit)

4.3  Universal asynchronous receiver/transmitter

4.4  SPI

4.5  PCI-Express - Overview

4.6  Transaction Layer in PCI Express

4.7  Microwire IP Interface 

5. Verilog Tutorial /Crash Course

5.1  Verilog Introduction

5.2  Refreshing your brain with Verilog

5.3  Verilog - Data Types 

5.4  Verilog - Statements  

5.5  Verilog Design Style

5.6  Verilog - System Task

5.7  Verilog Operators

5.8  Verilog - Reserved KeyWords

5.9  Parameterized Modules in Verilog

5.10 Timescale in Verilog

5.11 File Handling in Verilog 

5.12 Blocking and Non-Blocking in Verilog 

6. RTL Design Code 

6.1  Verilog Projects

6.2  RTL Verilog Code for Design

6.3  PCIe_Project_Update

6.4  Verilog Code for the counting number of 1's and 0's 

6.5  Verilog code for Asynchronous and Synchronous Reset Flip-Flop

6.6  Verilog code to detect Pattern

6.7  Verilog Code for Gray to Binary Code Converter

6.8  Verilog code for module 

6.9  Verilog code for FIR FILTER

6.10 Verilog code for parity checker (even parity/odd parity)

6.11 Verilog code square root of a number

6.12 Verilog Code for Round Robin Algorithm

6.13 Verilog Code for Binary to 7-segment LED converter 

6.14 Verilog Code for modules

6.15 Verilog Code for 8-bit ALU

6.16 Verilog Binary to gray code conversion

6.17 Verilog code and FSM design to generating custom waveform 

6.18 Verilog code for Synchronous FIFO ( First In First Out  )

7. Clock Domain Crossing (CDC)

7.1  Clock Domain Crossing (CDC)

7.2  Convergence , divergence and re-convergence

7.3  CDC - Real time implementation

8. RTL Lint 

8.1  SpyGlass Custom Goal setup

8.2  Synchronizers list dump using SpyGlass Tool

9. STA

9.1  Unateness-> Positive Unate and Negative Unate

9.2  VLSI_EXPERT: Transition Violation in Semiconductor

10. Synthesis

10.1  .lib to/from .db conversion

10.2 fanout report on hierarchy in design in synthesis 

10.3 Physical Aware Synthesis 

11. Integrated-Circuit Fabrication

11.1 IC Fabrication : Interview Questions / Answers 

12. AHB-AXI Protocol 

12.1 How do split response and retry work for the AHB protocol?

12.2 Comparing AMBA AHB to AXI Bus using System Modeling.

13. PCIe Protocol 

13.1  PCI-Express - Overview

13.2  Transaction Layer in PCI Express

13.3  8b10encoder/decoder

13.4  Running Disparity

14. Solution  :Samir Palnitkar : A Guide to Digital Design and Synthesis 

14.1 Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar 

15. Place holder5

16. DAA

16.1  Left Edge Channel Algorithm for detailed routing

16.2  Dynamic vs Static Timing Analysis

16.3  DAA: Design and Analysis of Algorithm 

16.4  DAA: Design and Analysis of Algorithm - QA 

17. Scripting/Others

17.1  GNOME - Terminal while login in VNC

17.2  Shell Script Tutorial

17.3  GVIM Help

17.4  List of Perl Scripts used in post data processing

18. Interview Preparation

18.1  VLSI Interview Questions

18.2  Generic interview Questions

18.3  Interview question on AXI protocol

18.4  Implementation of Logical Questions 

18.5 Digital Design Interview Question on PCIe express 

18.6  Digital Design Interview Question on Synthesis

 

19. Academic/ Educational Projects with Micro-Architecture and Verilog code

19.1  RoadMap For Academic Projects 

19.2  PCI-Express - Overview

19.3  Transaction Layer in PCI Express

19.4  Microwire IP  

20. Verification

20.1  Key Points in Mixed Signal Design Verification

21. Physical Design

21.1  What is the difference between a DRC and a DRV in VLSI PD?

21.2 Physical Design - Common Questions  

22. General Question:

22.1  Logical Question

22.2  APTITUDE Question for Interviews

22B . VLSI Quiz 

22B.1  Quiz1 : Digital Design

23. Non-VLSI Topics:

23.1  Worst Hiring Stories

23.2  You need to remove these 6 items from your resume asap

23.3  Resume Guideline if you are applying for job as a Freshers.

23.4  10 Things to remember while considering the offers from your next employer

23.5  Are you looking for job change ?

23.6  How to negotiate for the best when making a move from your present employer ?

23.7  where an engineer/fresher can get the job ?

23.8 How to start a academic project 

23.9  Team Leadership Score check 

23.10 Team Leadership Question/Answer

23.11 Being productive while working from home 

24. Salary Around the Globe

24.1 Norway Salary - Average salary for Senior Software Engineer in Norway with 10+ years experience? 

24.2  Sweden Salary - An Average salary in Sweden for IT professional  

25. Job Opportunities in Norway 

25.1  Norway Salary - Average salary for Senior Software Engineer in Norway with 10+ years experience? 

25.2  Is it hard to get a job in Norway, as a foreigner?

25.3  Living cost in Norway , compared with India

 

26. Finland Opportunities in IT Sector

26.1  Moving to Finland from India , is it worth ?

27. Funny Posts ( non technical )

27.1 40+ Photos That Evoke a Lot of Curious Questions and Can’t Be Explained

BIST - Built-in-self-Test

BIST generates its own stimulus and analyzes its own response.  BIST is used normally to validate a product in labs, there are different kind of BIST used in system to validate.
one of the method is , using LFSR, LFSR generates random stimulus and it is expected that chip is in its normal functional mode. with the configuration, with LFSR , one can validate the data path in system or in IP.


What is the motivation for BIST ? 
-> cost-efficient testing
-> stuck-at-fault model
-> cost of ATE (Automatic Test Equipment)



Types of BIST  

-> on-line BIST 
->  Concurrent on-line BIST 
Occurs simultaneously with normal functional operation , normally coding techniques or duplication and comparison are used.

           
 ->   Non-concurrent on-line BIST 
Carried out while in idle state , by executing software or firmware routines .

-> off-line BIST
System is not in its normal functional mode.

-> Functional off-line BIST 
It is based on a functional description of the circuit under test and uses functional high level fault models.
 

-> Structural off-line BIST 
Execution based on the structure of the circuit under test and used structural fault models.
Example -  Stuck-At-Fault  (SAF)  - cell stuck at constant value
                  Transition Fault  (TF)    - a cell which fails to go from 0->1 or 1->0  transition
                  Coupling Fault (CF)     - write operation to one cell changes the contents of a second cell

General Architecture of BIST 

Below is typical architecture of BIST testing , bist generator and bist collector would be inside DUT or outside DUT , depends on the BIST type.

LFSR Based Testing  : 

LFSR :  Linear Feedback Shift Register , hardware that generates psedo-random pattern for CUT (circuit under test)

BILBO : Built-In logic block observer , extra hardware need to convert flip-flop into scan chain in test mode.
Exhaustive Testing  : Apply all possible 2 (power of) n pattern to a circuit with n inputs , this will take more ATE time.

Pseudo-exhaustive testing:  Break circuit into small , overlapping blocks and test it.

Psudo Random test generation :

PRBS is basically a polynomial having a standard definition,  for exam - PRBS7, PRBS8, PRBS10, PRBS 31 ..

higher the number of PRBS, pattern will be more random and possibilities to hit a expected pattern in pattern generation will increased.

below is one example of implementation of polynomial, if you are more interested to go in more deep, send a email to me.



Ref -
http://en.wikipedia.org/wiki/Built-in_self-test
http://www.asic.co.in/ppt/BIST2.pdf