RTL DIGITAL DESIGN

Practical ASIC , RTL , VLSI Knowledge

Jul 10, 2016

Engineering Basics



Mathematics 

 Two's Complement
One's Complement
Complex Number
Type of Adders 

Digital Design

 MTBF
How to make XOR gate using NAND
NAND using Mux
Gates using Mux
Reset in Design
LockUP Latches
Parity Checker
Edge Detector
Clock Dividers
Clock Gating Circuit
CDC Basic -Part 1
Reset Recovery and Removal Time

Digital Signal Processing (DSP)
Protocol and Others

 SPI
UART
I2C
DLL and PLL

 SDC SampleFile
UPF Flow

Table of Contents
Posted by VLSI Expert - Rahul J
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