RTL Techniques to make device a Low Power Device

In my last blog , I have explain about the low power technique which includes rtl modification , cell selection, using UPF file, power saving at physical level , etc . During RTL implementation, a good designer can save a significant amount of power.

As we all knows power loss in chip is due to static power and dynamic power. During RTL implementation, we can not do anything on static power but we can save dynamic power by reducing number of transitions at gates. Below are few bullet points.

Power Saving during RTL Implementation 

1. One should write RTL in such  way where transition should be minimum , for example

always@(posedge clk or negedge reset) begin
 if(reset)
    data_out <= 64'd0;
 else if (latch_en)
   data_out <= data_in;
 else
   data_out <= 64'd0 ;
end

Above code can be written as shown below -

always@(posedge clk or negedge reset) begin
 if(reset)
    data_out <= 64'd0;
 else if (latch_en)
   data_out <= data_in;
end

If there is no need to reset data_out when latch_en is not high , then there is no harm to leave previous data on data bus, this will save lot of transition and will result in saving power.

2.  Implement clock gating for the blocks which are not required in some power state or in functional mode.
Clock gating is important if design intention is low power , one using clock gating, should use proper clock gating cells. Enable/disable signal of clock gating should be synchronized with respective clock domain to avoid glitches.

3.  In a design, there may be lot of counters , big or small ... to save power , those counters should not be free running counters. Use start and stop condition and run those counters whenever required.
Counters should be taken care in micro-architecture document, start/stop condition will be depend on certain condition which should be met.

4. Sharing logic will also help in reducing power as well as effective gate count.
Logic may get optimized during synthesis as tool is now having intelligence to detect same kind of logic and optimized them. But this will open a small confusion window as tool may or may not optimized the logic. It is always advised to share logic at RTL stage itself.

5.  If design having big state machine then prefer to use gray coding or one hot coding , In binary coding , transition will be more and will consume more power.

When you are working on micro-architecture of design, and if you want to make design as low power design then you need to think carefully about the transition. sometimes it might be possible that transitions are not in big numbers but when you save small numbers transitions multiple places then it will result in saving good amount of power.

The only disadvantage is , hardware will be more as you need to implement more logic and consumption of your mind power will be more as you need to think out of box to implement the logic. But at the end you will be called "expert in Low Power Design" which will open a lot of opportunities for your career and your future.

Let me know if I am missing something here , I can add here and make this article more effective. 

Thanks for your time. 

Rahul Jain