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Apr 28, 2022

Asynchronous FIFO Interview question

 

This is logical question. You have 2 block , block A and block B , talking to each other having synchronous fifo.  Both are in same clock domain. 



Now due to timing violation, designer is asked to insert pipeline and designer inserted 4 pipeline state. 





The question here is , what would be the minimum depth of FIFO so that we should not loss any data. 




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9 comments:

  1. AnonymousApril 28, 2022 at 10:26 AM

    Should it be existing FIFO depth -4 ?

    ReplyDelete
    Replies
    1. VLSI Expert - Rahul JMay 6, 2022 at 10:47 AM

      think about the fifo_full latency , by the time block-A knows that block-B fifo is getting full, there will be 4 data in pipeline.

      Delete
  2. AnonymousApril 28, 2022 at 8:36 PM

    Depth shouldn't change due to addition of pipelines.

    ReplyDelete
  3. SchooleducationDecember 29, 2022 at 12:59 PM

    can you provide the answer for the above?

    ReplyDelete
  4. AnonymousJanuary 13, 2023 at 3:28 PM

    Can you please provide write freq, read frea and burst size?

    ReplyDelete
  5. AnonymousApril 12, 2023 at 12:19 PM

    Will it be fifo_depth+4?

    ReplyDelete
  6. AnonymousAugust 18, 2023 at 8:09 PM

    FIFO_DEPTH of B must be 9

    ReplyDelete
  7. AnonymousSeptember 23, 2023 at 4:42 PM

    8

    ReplyDelete

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