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Dec 20, 2016

Verilog code square root of a number


Verilog code to calculate the square root of a number ->

------------------Start of Verilog Code --------------------

`timescale 1ns/100ps

module square_root (
  input [31:0] num,
  output reg[31:0] sqr_root,
  output reg sqr_root_integer
 
  );
 
  integer temp;
  reg [31:0] i;
 
  always @(*) begin
   sqr_root = 'b0;
   sqr_root_integer = 1'b0;
   for (i = 0 ; i < (num/2) ; i = i+1 ) begin
      temp = i*i ;
     if (temp  == num) begin
       sqr_root_integer = 1 ;
       sqr_root = i ;
     end
   end
 end
endmodule

module tb;
  reg [31:0] num_in=0;
  reg clk =0;
  wire integer sqrr;
  wire valid;

  always #1 clk = ~clk;
 
  always @(posedge clk) begin
    num_in = num_in +1 ;
  end
 
  square_root DUT (
  .num(num_in),
  .sqr_root_integer(valid),
  .sqr_root(sqrr)
  );
 
  always@(sqrr)
    if(valid)
    $display("Square root of number %d is %d ", num_in , sqrr);

endmodule


-------------------  End of Code -------------------

Simulation result -> 



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6 comments:

  1. This is just fine!
    But this is inefficient for calculation of square root of bigger numbers,isn't?

    ReplyDelete
  2. Is this code synthesizable? Reason why I’m asking is how do you know how many multiplier units you need?
    Or if you are using only 1 multiplier, how can you be deterministic about the combinational delay?

    ReplyDelete
  3. Is this code synthesizable? Reason why I’m asking is how do you know how many multiplier units you need?
    Or if you are using only 1 multiplier, how can you be deterministic about the combinational delay?

    ReplyDelete