These are threshold voltages, low vt, high vt and standard vt, the lower threshold voltage is the delay of this transistor is faster, but will have higher leakage power, vice versa.
Each standard cell is designed in multiple flavors of threshold voltage (Vt).
LVT → Low Vt cells
SVT → Standard Vt cells some times also referred as Nominal/Regular Vt cells
HVT → High Vt cells
Vt of a cell is altered by altering the channel doing of a MOS transistor.
As doing in the channel increases the gate threshold voltage increases because the gate voltage needs to deplete more majority carriers before a minority carrier channel can form.
Increasing order of channel doping
LVT→SVT→HVT
Increasing order of output drive current of a cell (of the same drive)
HVT→SVT→LVT
Cell delay reduce in this order
HVT→SVT→LVT
Cell leakage increases in this order
HVT→SVT→LVT
We typically allow Synthesis/PnR tools to use multiple Vt flavored cells.
Wherever tools need to reduce cell/net delays to meet setup timing in a timing path, it can use lower Vt cells. Otherwise would would use higher Vt cells to save leakage.
Vt Usage is clock tree ->
Clock network is the backone of VLSI chips on which everything relies for the better performance. Absolutely there has to be minimum variations to have consistent and predictable waveform at the end of the metal trace.
Standard cells with different vts are made with doping density differences. They have different suspentance to the physical phenomenon around the cell placed. Inorder to minimize the variations it's recommended to build the clk network with the same vt flavor.
Power consumption Table :
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