Retention Cells - UPF/ Low_power_mode

RETENTION CELLS - UPF - Low Power

FIG-1

Retention Cell Details :

These cells are special flops with multiple power supply. 

They are typically used as a shadow register to retain their value even if the block in which they are residing, is shut down.

FIG-1 is simple diagram of retention cells.

Types of Retention cells : 

1) Master/slave-alive retention: 

In a master/slave-alive retention register, the retained value is held in the master or slave latch. In this case, the retention element is in the functional data-path of the register.

2) Balloon-style retention: 

In a balloon-style retention register, the retained value is held in an additional latch, often called the  balloon latch. In this case, the balloon element is not in the functional data-path of the register.

Ballon-style retention can be Dual-Pin Retention cell or Single-Pin Retention cell.
Master/slave-alive retention is same as Zero-Pin Retention cell.


3) Dual-Pin Retention :
Dual-Pin Retention is the one which has two separate control signal for save and restore operation.
Save operation can be level-sensitive or edge-sensitive.

4) Single-Pin Retention:
Single-Pin Retention is the one which has single control signal for both save and restore operation.
Save operation can be level-sensitive or edge-sensitive.
Save operation and Restore operation will be on opposite level/edge of control signal. i.e If save is performed on level high than restore will be performed on level low of control signal.


Zero-Pin Retention:
Zero-Pin Retention is the one which does not have any control signal .
Save operation will be performed when the power domain in which cell is sitting goes from NORMAL to CORRUPT state.

Restore operation will be performed when the power domain in which cell is sitting goes from CORRUPT to NORMAL state.

UPF syntax to define Retention cells in a design:

set_retention 

  retention_strategy 

  -domain power_domain 

 [-retention_power_net retention_power_net] 

 [-retention_ground_net retention_ground_net] 

 [-retention_supply retention_supply_set] 

 [-no_retention] 

 [-elements objects] 

 [-exclude_elements exclude_objects] 

 [-save_signal {save_signal save_sense}] 

 [-restore_signal {restore_signal restore_sense}] 

 [-save_condition {boolean_function}] 

 [-restore_condition {boolean_function}] 

 [-retention_condition {boolean_function}] [-update] 

 [-use_retention_as_primary]


retention_strategy is name of retention strategy.

retention_power/grounds are retention power supply.

elements are the registers/cells/design hier which you want to put under retention.

Below is the retention circuit timing diagram. 

Do not confuse between isolation cells and retention cells, isolation cells are to drive a known value when circuit goes into power saving mode while retention cells retain the last value and drive the same when normal power is back.

One of the example is shown below. 

set_retention  dummy1_retention -domain VDD \

                 -retention_supply_set VDD_DPSLP \

                 -retention_condition { /DUT/design/signal1 } \

                 -elements {  reg1*

                                     reg2*

                                   }

map_retention_cell dummy1_retention \

  -domain VDD -lib_cells  CELL1 

This is one of the simple example to define the retention strategy. 

Labels:

Understanding of Retention cells
Understanding Low power checks
Special cells used for power planning.