Verilog code for parity checker (even parity/odd parity)

Verilog code for parity Checker -



In the case of even parity, the number of bits whose value is 1 in a given set are counted. If that total is odd, the parity bit value is set to 1, making the total count of 1's in the set an even number. If the count of ones in a given set of bits is already even, the parity bit's value remains 0.


In the case of odd parity, the situation is reversed. Instead, if the sum of bits with a value of 1 is odd, the parity bit's value is set to zero. And if the sum of bits with a value of 1 is even, the parity bit value is set to 1, making the total count of 1's in the set an odd number.

Odd Parity

1'b0  -  odd 1's
1'b1 -   even 1's

For Odd parity , if  input data is 1'b0 then odd parity should be 1'b1 , to make number of 1's odd , and if it is 1'b1 then odd parity should be 1'b0.

below is the code for it -

reg parity_chk_st;

always @(posedge clk or negedge rstn) begin
 if(!rstn)
    parity_chk_st <= 1'b0;
 else
   parity_chk_st <= parity_check;

assign parity_check =  parity_ch_st ^ parity_check;



Even Parity
1'b0  -> 1's are even
1'b1 -> 1's are odd , 1 to make one's even.