Lockup Latches

Q. What is Lockup Latch ?
A. A lockup latch is used to prevent data corruption caused by overwriting of new data over the present data before the clock edge occurs. i.e there is a potential problem of data coming early and overwriting the present actual which has to be fed.

In other words ,

Lockup latches are nothing more than transparent latches. You use them to connect two scan-storage elements in a scan chain in which excessive clock skew exists.

 Let a circuit contains two flip-flops. Flip-flop 1 represents the end of the scan chain that contains only elements that are in the clk1 clock domain. Flip-flop 2 represents the beginning of the scan chain that contains only elements that are in the clk2 clock domain. and these flip-flops have multiplexed inputs. The inputs of these flip-flops represent the scan inputs of the multiplexers. The latch has an active-high enable, which becomes transparent only when clk1 goes low and effectively adds a half clock of hold time to the output of flip-flop 1. In this figure, you assume that the system synchronously asserts clk1 and clk2, which would be the normal case during scan-mode operation. Although the clocks synchronously assert, some amount of clock skew between them still exists because they come from different clock trees.




lockup latches connect scan chains from different clock domains. However, you can just as easily use these latches to connect scan chains from various blocks within a chip that, although on the same scan chain, are physically remote from each other on the die. You want to make the latch transparent during the inactive part of the clock. For example, both flip-flops trigger on the rising edge of the clock. Therefore, you want to make the lockup latch transparent during the low period of the clock. If the flip-flops trigger on the falling edge of the clock, you want the latch to be transparent when the clock is high.


http://www.edn.com/article/CA46603.html




www.eetimes.com/document.asp?doc_id=1225378







During capture, design is in functional mode, hold time violation is solved by STA team during Functional timing closure.