Solution Exercise 7 : Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar

 1. Declare a register called oscillate, Initialize it to 0 and make it toggle every 30 time units. Do not use "always" statement. (hint: Use the forever loop )

Sol: 

reg oscillate ;
initial
oscillate = 0 ;

forever 

 #30 oscillate = ~oscillate ; 

..................

Sol 2. 

module test; 

reg clock ;

// Initialize clock to 0 

initial 

clock = 0 ;

// duty cycle 25% 

// 0 1 1 1  ->  time period is 10 

always  begin 

#10 clock = 0 ;

#10 clock = 1 ;

#10 clock = 1 ;

#10 clock = 1 ;

end 

endmodule 

---------

Sol3. 

a = 1'b0 

b = #10 1'b1 

c = #5 1'b0 ;

d = #20 (a,b,c)

Here , a will execute at 0ns 

b will execute after 10 time unit.

c will execute after 5 time unit. 

d will execute after 20 time unit. 

they are all blocking statement 

0ns     10 ns     15ns      35 ns 

a =0    b=1       c=1       d = 0,1,0 

---------

Sol 4. 

a <= 1'b0 

b <= #10 1'b1 

c <= #5 1'b0 ;

d <= #20 (a,b,c)

All statement will execute at 0ns , their values will be stored and will be assigned after respective time unit.

0ns  5ns 10 ns 20ns 

a=0  c=0  b=1   

d will be 'x' as at time 0 , a,b,c values were 'x' ( un-initialize) 

---------

Sol 5.

both initial block will execute at simulation time 0 in parallel.

a will be 0

c will be b and it will assign at the end of delta cycle  , b is assign to 1 so c will be assign to 1 at the end of 0ns time cycle.

b will be 1 

d will be a , assigned at the end of delta cycle , d will be 0 (a will execute first in 0ns time unit cycle)

---------

Sol 6. 

b,c would be assign at time 0 ns.

d will assign value at time 25ns , till that time, d value will be unknown.

--------

Sol 7.

module d_ff (  input clear, input clk, input d ,output  q  );

reg q ;

always @(negedge clk) begin

 if (clear)

  q <= 1'b0 ;

 else 

 q <= d ; 

end 

endmodule 

----------

Sol 8. 

module d_ff (  input clear, input clk, input d ,output  q  );

reg q ;

always @(negedge clk or posedge clear ) begin

 if (clear)

  q <= 1'b0 ;

 else 

 q <= d ; 

end 

endmodule 

----------

Sol 9.

module d_latch ( clk, d, q );

input clk ;

input d;

output q ;

always @(*) begin

wait (clk)

  q = d ; 

end 

endmodule 

-----------

example 7.14 

module mux4_to_1 ( out, i0, i1,i2,i3,s1,s0);

output out; 

input i0,i1,i2,i3;

input s1,s0 ;

always @(*) begin

if (s1 & s0 )  // 1 1 -> i3 

 out = i3 ;

else if (s1 & !s0)  // 1 0 -> i2 

 out = i2 ;

else if (!s1 & s0)  // 0 1 -> i1 

 out = i1 ;

else if (!s1 & !s0)  // 0 0 -> i0

 out = i0;

end 

endmodule 

-------