Max transition (clock or data) is the maximum slew that is allowed at the cell input pin.
This comes either from the library, or it can come from a manually constrained file from the designer.
Similarly, max capacitance check limits the allowed capacitance on the output pin of a cell.
The transition time of a net becomes the time required for its driving pin to change logic values (from 10% (20%) to the 90% (80%) of its maximum value). This transition time used for delay calculations are based on the timing library (.lib files).
Input transition and output load are used to characterize delay through a circuit. Typically, a circuit is simulated under many different process, temperature and voltage conditions over a range of input transitions and output loads to characterize circuit performance. Some design teams prefer to model very accurate delays over a tight range of variables while others can afford to sacrifice some accuracy to accommodate a wider range of performance, e.g. a NAND gate simulated over input transitions from 5ps to 90ps and output loads from 3fF to 200fF could have a more accurate result than one characterized over 0ps to 1ns inputs and 0fF to 1pF outputs.
These are important checks in the timing drcs. Max transition (clock or data) is the maximum slew that is allowed at the cell input pin.This comes either from the library, or it can come from a manually constrained file from the designer.
Similarly, max capacitance check limits the allowed capacitance on the output pin of a cell.
Flagging these and fixing them help with lower dynamic leakage (short circuit current) and reaching more reliability.
Fixing Transition Violation
1. Up sizing the driver cell.
2. Decreasing the net length by moving cells nearer or reducing long routed net.
3. By adding buffers.
4. By using existing spare cells as buffers.
5. By splitting loads through buffers to reduce the fan out number (number of driven cells)
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