Digital Design for Beginners and Professionals

VLSI Interview Questions ->>>

First Question before starting anything on VLSI or Digital design ....


Are you new to semiconductor ?   
If your answer is  "No" then there is lot of scope to learn in semiconductor which really depends on your interest. Sometime it happens , you have to work on those module which you do not want , but it happens and you should take it in easy and with positive attitude. Even with that work , you can learn a lot of things.

But for above question , if your answer is "Yes" then you need to go though the basic VLSI where CMOS/ npn/ pnp transistor comes in picture. learn how semiconductor device work.

There are few basic skills which are expected from a Digital designer or verification engineer. 




For Design - 



1. Digital fundamentals 
2. Knowledge on building micro-architecture
3. RTL coding , knowledge of any HDL (Verilog or VHDL) 
4. Tool knowledge like ModelSim, Questa, Cadence simulator , VCS 

There are many ways to improve design flow and turn around time to come up with updated and strong design. please see below few points. 

1. If  design is already ported , then one should think of optimizing the logic and should think to reduce gate count with same functionality.
2. If lint and cdc have not run , then work on lint and cdc environment and pass your design through lint and cdc. If you run it at block level, it will be fast and fixing time will be very less, but one should not forget to run at top level, there could be human error while integrating the different blocks .
  
For Verification - 

Today, system verilog is getting used in verification, this SVL giving flexibility to users to drive random stimulus, reusable components and giving a very good command to verify DUT. 

But still a verification engineer should be having good knowledge of design which he/she verifying and always try to think to crack the design. Most of designs are now porting kind of design which having verification environment also and it is very difficult to find a  bug in such design until or unless you are very good verification engineer but there are always a scope of improvement. 

Verification engineer can think of below points.
1. Implementing more checkers (automated way)
2. Coverage analysis on DUT, if it is already done then try to achieve 100% coverage with    waivers.
3. Assertion implementation 
4. Feature list documentation, using that they can generate a top level graph for management to measure the progress,  we have Questa now having verification management and able to generate such kind of reports to management. 
5. Try to make environment in more automated way
6. One thing which is really really very difficult to implement in environment , is model the interface timing such that interface looks like a real silicon. This will not help in functional simulation but will help in gate level simulation. 



Debugging simulation is also in-built art which comes naturally being a engineer.
I have put some points in below link. 

How To debug a simulation


Other Topics -
Contents
Refreshing your brain with Verilog 
Digital Design of Hybrid Memory Cube
Correct way of  Digital design RTL Coding
Clock Gating Circuits
Digital Design Interview Question
Knowledge on Verification

More are yet to come , all comments and suggestions are welcome and will help to put information here.  
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