Verilog - Data Types

Verilog HDL consists of 4 basic values -
0 - Logic zero
1 - Logic one
x - unknown value
z -high-impedance state

value z and x are same, notable exception are the primitives which can pass the z value.

Nets and Registers 
The net data types represent the physical connections, a net does not store a value (except trireg net).
Register type will store the value from assignment.

Declaring reg and net types -

reg [N-1:0] <reg_name1> , <reg_name2> ;

declaring N-bit register named reg_name1 and reg_name2

wire [N-1:0] <wire_name1> , <wire_name2>;

declaring N-bit wire named wire_name1 and wire_name2

tri [N-1:0] tri_name ;
A tri state tri_name signal with N-bit

One can declare integer , time , real type of variables.

Declaration of memory -

reg [3:0] mem [4:0] ;

This will create memory of 5 registers of 4-bit each.


Parameters 

Parameters are not reg type or wire type, all parameter declaration is a constant.
syntax to declare parameter -
parameter abc = 1;
parameter x =10, y = 12;
parameter z = expression (abc) ;   // abc should be a constant value

NEXT

Pages which you would like to visit -
Verilog Overview
Brain refreshment through Verilog 

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Rahul Jain