Timescale in Verilog

Time Scale And Time Precision:

Delay unit is specified using 'timescale, which is declared as `timescale time_unit base / precision base

--time_unit is the amount of time a delay of #1 represents. The time unit must be 1 10 or 100
--base is the time base for each unit, ranging from seconds to femtoseconds, and must be: s ms us ns ps or fs
--precision and base represent how many decimal points of precision to use relative to the time units.

For example : `timescale 1 ns / 100 ps means

time values to be read as ns and to be rounded to the nearest 100 ps.
If timescale is omitted, there is a default time scale.

The following examples demonstrate how the time scale and time precision effect $stime, #delay and toggling in waveform.

`timescale 1ns/1ps

means ur time scale is ns with resolution OR least count of 1ps

#1 ; // 1ns delay

#0.001; // 0.001 ns this is the minimum delay you can have with this time scale!

#0.0001; // this will give 0 ns delay!!

Hope these example helps you understand the verilog timescale!!

let's consider

`timescale 1ns/1ps

reg set;
parameter d = 1.55
initial
begin
#d set = 0;
#d set = l;
end
endmodule

The `timescale tells the system to use 1 ns for all reporting and internally use 1 ps for resolution of time in this part of design. Thus, the value for parameter d is scaled to a delay of 1.55 ns. Had we used timescale directive `timescale 10ns/1ns, 1.55 would mean 15.5 or 16 ns. The first part of `time-scale gives the time-units and the second part gives the time-precision.