Verilog Introduction

Verilog is a HDL language, HDL – Hardware Description Language , which means any digital hardware can be described by verilog language. It is a standard format which simulators and synthesis tools are used to understand digital logic written in Verilog.


For example – D Flop


-----------------------------------D Flip Flop ------------------------
module d_ff (


input d,
input clk, reset,
input en,


output q
);


always @(posedge clk or negedge reset) begin
if(reset)
q <= 1'b0;
else if (en)
q <= d ;
end


endmodule
-------------------------------------------------------------------------


Verilog is not like a 'C' language, it is totally different than other language used in software.


Brief history


Verilog was developed at a time when designers were looking for tools to combine different levels of
simulation. In the early 1980s, there were switch-level simulators, gate-level simulators, functional
simulators (often written ad-hoc in software) and no simple means to combine them. Further, the
more-widespread, traditional programming languages themselves were/are essentially sequential and
thus "semantically challenged" when modelling the concurrency of digital circuitry.
Verilog was created by Phil Moore in 1983-4 at Gateway Design Automation and the first simulator
was written a year later. It borrowed much from the existing languages of the time: the concurrency
aspects may be seen in both Modula and (earlier) Simula; the syntax is deliberately close to that of C;
and the methods for combining different levels of abstraction owe much to Hilo (from Brunnel
University, UK).
In 1989, Gateway Design Automation (and rights to Verilog) were purchased by Cadence who put
Verilog in the public domain in the following year. This move did much to promote the use of Verilog
since other companies were able to develop alternatives tools to those of Cadence which, in turn,
allowed users to adopt Verilog without dependency on a single (primarily workstation-tool) supplier.
In 1992, work began to create an IEEE standard (IEEE-1364) and in December 1995 the final draft
was approved. Thus Verilog has become an international standard - which will further increase its
commercial development and use.
At present, there is standards activity to extend Verilog beyond purely digital circuits. This includes
Verilog-MS for "mixed signal specification" and Verilog-A for "analog" design; the latter was recently
approved (June 1996) by the board of Open Verilog International and is now under consideration by
the IEEE. In addition, work is underway to automate the proof of "equivalence [between] behavioural
and synthesizable specifications" (see the Cambridge web site below) to which Verilog readily lends itself.
While Verilog emerged from developments within private companies, its main rival came from the
American Department of Defence (DoD). In 1981, the DoD sponsored a workshop on hardware
description languages as part of its Very High Speed Integrated Circuits (VHSIC) program, and the
outcome formed a specification for the VHSIC hardware description language (VHDL) in 1983.
Because this was a DoD programme, there were initially restrictions its dissemination, until 1985
when the development was passed on to IEEE whose standard (IEEE 1076) was formally accepted in
1987.
There is, of course, the question as to which language is better. And this, of course, is a hard question
to answer without causing excitement and rebuttals from the marketing departments of the less preferred
language. However, the following points featured in a recent debate in the VHDL and
Verilog news groups.
The main factor is the language syntax − since Verilog is based on C and VHDL is based on ADA:
• Verilog is easier to learn since C is a far simpler language. It also produces more compact code:
easier both to write and to read. Furthermore, the large number of engineers who already know
C (compared to those who know ADA) makes learning and training easier.
• VHDL is very strongly typed, and allows programmer to define their own types although, in
practice, the main types used are either the basic types of the language itself, or those defined by
the IEEE. The benefit is that type checking is performed by the compiler which can reduce
errors; the disadvantage is that changing types must be done explicitly.
Verilog has two clear advantages over VHDL:
• it allows switch-level modelling - which some designers find useful for exploring new circuits
• it ensures that all signals are initialized to "unknown" which ensures that all designers will
produce the necessary logic to initialize their design - the base types in VHDL initialize to zero
and the "hasty" designer may omit a global reset
VHDL has two clear advantages over Verilog:
• it allows the conditional instancing of modules ( if/for ... generate ). This is one of those
features that you do not miss until you have used it once - and then you need it all the time.
Many Verilog users recognize this lack and create personal pre-processing routines it implement
it (which negates some of the advantages of a language standard).
• it provides a simple mechanism (the configure statement) which allows the designer to switch
painlessly between different descriptions of a particular module. The value of this is described
in the next section.
Selecting a design language, however, cannot be done by considering the languages in isolation.
Other factors must include the design environment, the speed of simulation and the ease with which
the designer can test-and-debug the code: the design environment is crucial. Verilog includes the
Programming Language Interface (PLI) which allows dynamic access to the data structure. For the
expert user this gives a degree of control which few simulators (if any) can match. For the tooldesigner
it encourages the development of better design environments with tools such as customized
graphical waveform displays, or C-language routines to dynamically calculate delays for timing
analysis.
Pragmatically, both languages have a large installed base and design-investment − thus a designer
needs to know both. However, the market place is now being won by Verilog: the latest figures
(EDAC’s market research) give Verilog a nearly 2:1 lead over VHDL in tools’ revenue.

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