fanout report on hierarchy in design in synthesis

 

The fanout you can set on IO , but if you want to know the fanout of clock gating  assuming design have the clock gating to save power, in this case, one clock gate may drive many flip flops .

report clock_gating -fanout_histogram -instance  <instance_name> 

This command will give you histogram of clock gating , an example it below.

If you do not give instance name then by default it will be performed on current design. 

This is for Genus (Cadence) , Probably it would be same for the DC also.

Table of Contents

Digital Design Interview Question on Synthesis