Table of Contents

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CONTENTS

1.Introduction : 

1.1  Career Growth in VLSI Industry

1.2  The Future of Semiconductor 

2. VLSI Topics

2.1  Semiconductor Job Portal - Intern & freshers  

2.2  Digital Design for Beginners and Professionals

2.3  Career Growth in VLSI Industry

2.4  The Future of Semiconductor 

2.5  Reason for limited entry scope for Freshers in VLSI

2.6  VLSI Industry Update

2,7  List of Semiconductor Companies

2.8  Top 10 VLSI companies

2.9  VLSI Industry Updates

2.10 Engineering Basics

2.11 Open Sourced FREE CAD/EDA VLSI tools 

2.12 List of top 10 companies in Semiconductor - 2021 

2.13 The best top 20 universities for MS in Digital VLSI in USA

2.14 Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar 

2.15 Question Answer on VLSI Semiconductor 

 3. Digital Design:

3.1  Low Power Design Technique

3.2  Reset Removal and Recovery Time 

3.3  AND , OR gate using 2:1 Mux

3.4  Draw a  2 input NAND gate using 2:1 mux

3.5  Low Power design and verification

3.6  Which gate power consumption better than reversible logic gate?

3.7  UPF Example 

3.8  SDC File -  A Sample file for Synthesis

3.9  Pos n Neg edge detector

3.10 Lockup Latches

3.11 Selective Signal dumping in VPD VCS

3.12 Async Reset or Sync Reset for ASIC ?

3.13 Digital PLL

3.14 Complex Number

3.15 DLL and PLL

3.16 How to make XOR gate using NAND

3.17 What is MTBF ?

3.18 One's Complement

3.19 Two's Complement

3.20 Error Correction and Detection - SECDEC

3.21 Running Disparity

3.22 Open Sourced FREE CAD/EDA VLSI tools 

3.23 Type of Adders with Verilog Code

3.24 VHDL operator 

3.25 Asynchronous FIFO with Programmable Depth

3.26 Asic Implementation Design Cycle 

3.27  Comparing AMBA AHB to AXI Bus using System Modeling. 

3.28 Difference between I2C or CAN protocol ? 

3.29  Retention Cells - UPF

4. Semiconductor Interface/Bus Protocols

4.1  List of Protocols (PCIe, USB , etc.)

4.2  I²C (Inter-Integrated Circuit)

4.3  Universal asynchronous receiver/transmitter

4.4  SPI

4.5  PCI-Express - Overview

4.6  Transaction Layer in PCI Express

4.7  Microwire IP Interface 

5. Verilog Tutorial /Crash Course

5.1  Verilog Introduction

5.2  Refreshing your brain with Verilog

5.3  Verilog - Data Types 

5.4  Verilog - Statements  

5.5  Verilog Design Style

5.6  Verilog - System Task

5.7  Verilog Operators

5.8  Verilog - Reserved KeyWords

5.9  Parameterized Modules in Verilog

5.10 Timescale in Verilog

5.11 File Handling in Verilog 

5.12 Blocking and Non-Blocking in Verilog 

6. RTL Design Code 

6.1  Verilog Projects

6.2  RTL Verilog Code for Design

6.3  PCIe_Project_Update

6.4  Verilog Code for the counting number of 1's and 0's 

6.5  Verilog code for Asynchronous and Synchronous Reset Flip-Flop

6.6  Verilog code to detect Pattern

6.7  Verilog Code for Gray to Binary Code Converter

6.8  Verilog code for module 

6.9  Verilog code for FIR FILTER

6.10 Verilog code for parity checker (even parity/odd parity)

6.11 Verilog code square root of a number

6.12 Verilog Code for Round Robin Algorithm

6.13 Verilog Code for Binary to 7-segment LED converter 

6.14 Verilog Code for modules

6.15 Verilog Code for 8-bit ALU

6.16 Verilog Binary to gray code conversion

6.17 Verilog code and FSM design to generating custom waveform 

6.18 Verilog code for Synchronous FIFO ( First In First Out  )

 6.19 SPI Controller 

7. Clock Domain Crossing (CDC)

7.1  Clock Domain Crossing (CDC)

7.2  Convergence , divergence and re-convergence

7.3  CDC - Real time implementation

8. RTL Lint 

8.1  SpyGlass Custom Goal setup

8.2  Synchronizers list dump using SpyGlass Tool

9. STA

9.1  Unateness-> Positive Unate and Negative Unate

9.2  VLSI_EXPERT: Transition Violation in Semiconductor

10. Synthesis

10.1  .lib to/from .db conversion

10.2 fanout report on hierarchy in design in synthesis 

10.3 Physical Aware Synthesis 

10.4 SDC file for DDR memory 

11. Integrated-Circuit Fabrication

11.1 IC Fabrication : Interview Questions / Answers 

12. AHB-AXI Protocol 

12.1 How do split response and retry work for the AHB protocol?

12.2 Comparing AMBA AHB to AXI Bus using System Modeling.

13. PCIe Protocol 

13.1  PCI-Express - Overview

13.2  Transaction Layer in PCI Express

13.3  8b10encoder/decoder

13.4  Running Disparity

14. Solution  :Samir Palnitkar : A Guide to Digital Design and Synthesis 

14.1 Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar 

15. Place holder5

16. DAA

16.1  Left Edge Channel Algorithm for detailed routing

16.2  Dynamic vs Static Timing Analysis

16.3  DAA: Design and Analysis of Algorithm 

16.4  DAA: Design and Analysis of Algorithm - QA 

17. Scripting/Others

17.1  GNOME - Terminal while login in VNC

17.2  Shell Script Tutorial

17.3  GVIM Help

17.4  List of Perl Scripts used in post data processing

18. Interview Preparation

18.1  VLSI Interview Questions

18.2  Generic interview Questions

18.3  Interview question on AXI protocol

18.4  Implementation of Logical Questions 

18.5 Digital Design Interview Question on PCIe express 

18.6  Digital Design Interview Question on Synthesis

 

19. Academic/ Educational Projects with Micro-Architecture and Verilog code

19.1  RoadMap For Academic Projects 

19.2  PCI-Express - Overview

19.3  Transaction Layer in PCI Express

19.4  Microwire IP  

20. Verification

20.1  Key Points in Mixed Signal Design Verification

21. Physical Design

21.1  What is the difference between a DRC and a DRV in VLSI PD?

21.2 Physical Design - Common Questions  

21.3 FILLER CELLS  

22. General Question:

22.1  Logical Question

22.2  APTITUDE Question for Interviews

22B . VLSI Quiz 

22B.1  Quiz1 : Digital Design

23. Non-VLSI Topics:

23.1  Worst Hiring Stories

23.2  You need to remove these 6 items from your resume asap

23.3  Resume Guideline if you are applying for job as a Freshers.

23.4  10 Things to remember while considering the offers from your next employer

23.5  Are you looking for job change ?

23.6  How to negotiate for the best when making a move from your present employer ?

23.7  where an engineer/fresher can get the job ?

23.8 How to start a academic project 

23.9  Team Leadership Score check 

23.10 Team Leadership Question/Answer

23.11 Being productive while working from home 

24. Salary Around the Globe

24.1 Norway Salary - Average salary for Senior Software Engineer in Norway with 10+ years experience? 

24.2  Sweden Salary - An Average salary in Sweden for IT professional  

25. Job Opportunities in Norway 

25.1  Norway Salary - Average salary for Senior Software Engineer in Norway with 10+ years experience? 

25.2  Is it hard to get a job in Norway, as a foreigner?

25.3  Living cost in Norway , compared with India

 

26. Finland Opportunities in IT Sector

26.1  Moving to Finland from India , is it worth ?

27. Funny Posts ( non technical )

27.1 40+ Photos That Evoke a Lot of Curious Questions and Can’t Be Explained

I2C Timing Constraint Examples

Timing Constraint for I2C interface :
The I2C protocol is explained well @I2C_Protocol page ,with the protocol knowledge , one should also be knowing how to constraint the I2C interface and close timing on it's interface. 

Timing Constraint for SPI interface:

I2C timing constraints refer to the timing requirements for the communication between the master and slave devices in an I2C bus. These constraints are critical to ensuring proper operation of the bus. The key timing parameters involved in I2C communication are:

1. SCL (Serial Clock Line) Timing

• SCL High Time (T_high): The minimum time the SCL line must stay high between clock pulses.
• SCL Low Time (T_low): The minimum time the SCL line must stay low between clock pulses.
• SCL Rise Time (T_r): The time it takes for the SCL line to rise from a low to a high state.
• SCL Fall Time (T_f): The time it takes for the SCL line to fall from a high to a low state.

2. SDA (Serial Data Line) Timing

• SDA Hold Time (T_sda_hold): The minimum time that the SDA line must remain stable after the clock pulse edge.
• SDA Setup Time (T_sda_setup): The minimum time that the SDA line must remain stable before the clock pulse edge.
• SDA Rise Time (T_rise): The time it takes for the SDA line to rise from low to high.
• SDA Fall Time (T_fall): The time it takes for the SDA line to fall from high to low.

3. Start and Stop Conditions

• Start Condition (T_start): The timing of the transition from high to low on SDA while SCL is high, indicating the beginning of communication.
• Stop Condition (T_stop): The timing of the transition from low to high on SDA while SCL is high, indicating the end of communication.

4. Bus Free Time (T_buf)

• This is the time required between the stop condition of one transmission and the start condition of the next transmission. It ensures that the bus is idle and free for the next communication.

5. Data Validity

• Data Setup Time (T_data_setup): The time that data on SDA needs to be stable before the clock pulse edge to ensure that it is reliably read by the receiver.
• Data Hold Time (T_data_hold): The time that data on SDA needs to remain stable after the clock pulse edge to avoid corruption of data.

Common Values (Typical I2C speed: 100 kHz, 400 kHz)

• SCL High Time (T_high): > 4.7 µs for 100 kHz, > 1.3 µs for 400 kHz.
• SCL Low Time (T_low): > 4.7 µs for 100 kHz, > 1.3 µs for 400 kHz.
• SCL Rise Time (T_r): ≤ 1000 ns.
• SCL Fall Time (T_f): ≤ 300 ns.
• SDA Setup Time (T_sda_setup): ≥ 250 ns.
• SDA Hold Time (T_sda_hold): ≥ 200 ns (minimum after the clock edge).

Important Considerations:

• These timings depend on the specific I2C standard used (Standard-mode, Fast-mode, Fast-mode Plus, High-Speed mode).
• The tolerances for these timings will be dependent on the clock frequency of the bus. For example, with higher clock speeds (like 400 kHz), the timing constraints are more strict than for slower speeds (like 100 kHz).
• The capacitance on the bus and the drive strength of the devices involved can affect these timing values, especially for the rise and fall times.

Great! Let's go over a few common calculations or scenarios for I2C timing constraints, particularly focusing on parameters like rise time, fall time, and bus speed.

Example 1: Rise and Fall Time Calculation

For I2C, the rise time and fall time depend on the pull-up resistors and the capacitance of the bus. Here’s the basic formula to calculate the rise time:

$$T_r = 0.8473 \times R_{\text{pull-up}} \times C_{\text{bus}}$$

Where:

• $T_r$ = rise time in seconds
• $R_{\text{pull-up}}$ = pull-up resistor value in ohms (Ω)
• $C_{\text{bus}}$ = bus capacitance in farads (F)

Example Calculation:

Let’s say you have the following parameters:

• Pull-up resistor $R_{\text{pull-up}} = 4.7 \, k\Omega$
• Bus capacitance $C_{\text{bus}} = 20 \, pF$

Using the formula:

$$T_r = 0.8473 \times 4700 \times 20 \times 10^{-12}$$

Let me calculate that for you!

Example 2: Data Setup and Hold Times

The setup time (T_setup) is the time the data line (SDA) needs to be stable before the clock line (SCL) changes, and hold time (T_hold) is the time the data line needs to stay stable after the clock edge.

Typically:

• Setup time $T_{\text{setup}}$ is often specified as at least 250 ns.
• Hold time $T_{\text{hold}}$ is typically 200 ns or more.

If your device needs to meet specific constraints, you should ensure the time between clock pulses (SCL) and data (SDA) lines meets the minimum requirements.

The constraints (timing requirements) ensure that the data is transmitted reliably between the master and the slave devices. These constraints govern the timing of signals on the SDA (data line) and SCL (clock line). Below are the key timing constraints for I2C communication at Standard mode (100 kHz) and Fast mode (400 kHz):

Key I2C Timing Constraints

1. SCL Clock Frequency:

   • Standard Mode (100 kHz):
     • Maximum frequency: 100 kHz.
   • Fast Mode (400 kHz):
     • Maximum frequency: 400 kHz.

2. SCL Timing:

   • SCL High Time (T_high):
     • Standard Mode: ≥ 4.7 µs.
     • Fast Mode: ≥ 1.3 µs.
   • SCL Low Time (T_low):
     • Standard Mode: ≥ 4.7 µs.
     • Fast Mode: ≥ 1.3 µs.
   • SCL Rise Time (T_rise):
     • Standard Mode: ≤ 1000 ns.
     • Fast Mode: ≤ 300 ns.
   • SCL Fall Time (T_fall):
     • Standard Mode: ≤ 300 ns.
     • Fast Mode: ≤ 300 ns.

3. SDA Timing:

   • Data Hold Time (T_sda_hold):
     • Minimum: 200 ns after the SCL clock edge.
   • Data Setup Time (T_sda_setup):
     • Minimum: 250 ns before the SCL clock edge.
   • SDA Rise Time (T_rise):
     • Same as SCL Rise Time: ≤ 1000 ns for Standard Mode, ≤ 300 ns for Fast Mode.
   • SDA Fall Time (T_fall):
     • Same as SCL Fall Time: ≤ 300 ns.

4. Start and Stop Conditions:

   • Start Condition Setup Time (T_start):
     • Minimum: 4.7 µs.
   • Stop Condition Setup Time (T_stop):
     • Minimum: 4.7 µs.

5. Bus Free Time (T_buf):

   • Minimum time the bus must remain idle before the next Start Condition:
     • 4.7 µs.

6. Data Validity:

   • Data Setup Time (T_data_setup):
     • Data on SDA must be stable for 250 ns before the clock edge.
   • Data Hold Time (T_data_hold):
     • Data on SDA must remain stable for 200 ns after the clock edge.

7. Total Data Transfer Time (for a given number of bits):

   • The time it takes to transfer one bit of data depends on the clock frequency. At 100 kHz: $$T_{\text{bit}} = \frac{1}{100 \, kHz} = 10 \, \mu s$$
   • Similarly, for 400 kHz: $$T_{\text{bit}} = \frac{1}{400 \, kHz} = 2.5 \, \mu s$$

Key Timing Diagram

Here’s a general overview of how the key signals and constraints behave over time:

1. Start Condition (S): The SDA line is pulled low while SCL is high.
2. Data Bit Transfer: SDA is driven low or high while SCL pulses.
3. Stop Condition (P): The SDA line is pulled high while SCL is high.
4. Idle State: Both SDA and SCL are high, and the bus is free.

Example: Timing Calculation for a 100 kHz I2C Clock

• For 100 kHz (Standard Mode):

  • SCL High Time (T_high): ≥ 4.7 µs.
  • SCL Low Time (T_low): ≥ 4.7 µs.
  • T_bit (Time per Bit): 10 µs.

• For 400 kHz (Fast Mode):

  • SCL High Time (T_high): ≥ 1.3 µs.
  • SCL Low Time (T_low): ≥ 1.3 µs.
  • T_bit (Time per Bit): 2.5 µs.

Summary of Critical Timing Values

Parameter	Standard Mode (100 kHz)	Fast Mode (400 kHz)
SCL High Time (T_high)	≥ 4.7 µs	≥ 1.3 µs
SCL Low Time (T_low)	≥ 4.7 µs	≥ 1.3 µs
SCL Rise Time (T_rise)	≤ 1000 ns	≤ 300 ns
SCL Fall Time (T_fall)	≤ 300 ns	≤ 300 ns
SDA Setup Time (T_sda_setup)	≥ 250 ns	≥ 250 ns
SDA Hold Time (T_sda_hold)	≥ 200 ns	≥ 200 ns
Start Condition (T_start)	≥ 4.7 µs	≥ 4.7 µs
Stop Condition (T_stop)	≥ 4.7 µs	≥ 4.7 µs
Bus Free Time (T_buf)	≥ 4.7 µs	≥ 4.7 µs

Constraints to Remember:

• Clock speed is one of the most important factors influencing timing constraints. Higher clock speeds (e.g., 400 kHz vs 100 kHz) demand stricter rise and fall times, as well as tighter setup and hold times for data signals.
• Bus capacitance and pull-up resistor values can also affect timing (especially for rise/fall times).
• SDA and SCL lines must meet setup and hold times relative to each other to avoid data corruption or errors in transmission.

These constraints help to ensure reliable communication, and violating them may result in incorrect data transfer, bus contention, or timing errors.

.lib to/from .db conversion

If you are working in DC then all library files will be in .db format , this format is nit readable by humans.

You need to convert .db file to .lib file. For that you need library compiler and license for it.

Below are the commands used to get .lib file.

Both dc_shell (Design Compiler) and Library Compiler (lc_shell)
can do this translation.

--------------------------------------------------------------------------
lc_shell> read_lib ...
lc_shell> write_lib ...

Use "read_lib", then "write_lib", of course you need a library compiler license.
You CAN NOT use those commands from DC if you
dont have a library compiler license.

Convert from .lib to .db -> 

Yes.You can use library_compiler to convert your libary from lib format to db format.
%dc_shell
dc_shell>read_lib ./path/library_file_name.lib(ex: ABCD.lib)
dc_shell>write_lib library_name -f db -o ./path/library_file_name.db

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